Discussion Overview
The discussion centers on the reasons behind the high input impedance of Field Effect Transistors (FETs), including specific considerations for MOSFETs and JFETs. Participants explore the mechanisms contributing to this characteristic and compare it to bipolar transistors.
Discussion Character
- Technical explanation
- Conceptual clarification
- Debate/contested
Main Points Raised
- One participant suggests that the high input impedance of FETs is due to the reverse voltage applied at the gate, which reverse-biases the P-N junction.
- Another participant explains that in MOSFETs, the high impedance arises from the isolation layer (SiO2) between the gate and channel, resulting in minimal leakage current compared to bipolar transistors.
- A participant questions the input impedance of JFETs, noting the absence of an insulating layer between the gate and channel.
- It is mentioned that JFETs utilize a narrow piece of high resistivity semiconductor material to form the channel, with doping affecting current flow.
- Another participant clarifies that JFETs have a reverse-biased diode between the gate and channel, allowing only small leakage current to flow into the gate, which is still lower than the base current in BJTs.
Areas of Agreement / Disagreement
Participants express differing views on the mechanisms contributing to the high input impedance of JFETs compared to MOSFETs, indicating that multiple competing explanations exist without a clear consensus.
Contextual Notes
Some assumptions about the operation of FETs and the comparison to BJTs are not fully explored, and the discussion does not resolve the nuances of input impedance across different FET types.