JFET current source: why does the top transistor need higher IDSS?

[marc.orr]

Hello, I'm trying to brush up on my analog electronics a bit. I've been studying "The Art of Electronics".

In chapter 4 they show a jfet current source. It consists of two nfets. The source of the top one is connected to the drain of the bottom one. Both have their gates connected to ground. The bottom fet has its source connected to ground through a resistor. The drain of the top fet is where the load is connected.

It seems pretty straightforward. I just don't understand the calculations of it.

1) First of all, the book says that IDSS has to be larger for the top transistor than for the bottom one. Why is this?

2) General FET calculation question: In a bjt you know that there is a .7 volt drop between base and emitter and this makes calculations very straight forward. For the FET, i understand that the drain and source current depend on the voltage between the gate and the source. How do you know the voltage at the source?

Thanks for everyone's time.

-Marc Orr

 

[SGT]

For the bottom FET the source is connected to ground, so the gate-source voltage is zero and that is why the FET current is IDSS (Drain current with gate-source short circuited). This is the current source.
The upper FET is operating normally. Its source has a positive voltage and its gate is grounded, so Vgs < 0. It seems that it operates as a buffer between the current source and the load.