LT spice result analysis, Capacitance Multiplier vs RC filter circuit

AI Thread Summary
The discussion focuses on the simulation results of an RC filter circuit versus a capacitance multiplier (CM) circuit, aiming to validate that the CM circuit should yield lower output current (Iout) and ripple voltage (Vp-p). Contrary to expectations, the results show that the CM circuit has a higher Iout and Vp-p than the RC filter, raising questions about the simulation setup. Participants suggest simplifying the comparison by merging the circuits into one file and addressing potential issues with the circuit configuration, such as using two voltage sources in series and the choice of transistor model. Additionally, it is noted that the frequency analysis may be flawed, as the fundamental frequency of a full-wave rectified signal is 100 Hz, not 50 Hz. The discussion highlights the need for careful consideration of circuit design and simulation parameters to achieve accurate results.
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Hi friends,

I have simulated two circuits, one is an RC filter and other is a Capacitance multiplier.
My aim of experiment is to validate a decrease in Iout (load current) of CM circuit as compared to load current in RC filter circuit.

Theoretically,
Iout (CM circuit) < Iout (RC filter)
Vp-p (CM circuit) < Vp-p (RC filter)

My results:
1.RC filter

Vout (dc) = 0.0458716 ( .op 300ms)
Iout (dc) = 0.00458716

Vout (ac) = 43.7 ~ 48 mV (.tran 300ms)
Iout (ac) = 4.80 ~ 4.37 mA

Vp-p (ripple) = 0.00437018 (.meas)

2.CM circuit


Vout (dc) = 0.323751
Iout (dc) = 0.0323751
Vout (ac) = 322 ~ 327 mV
Iout (ac) = 32.65 ~ 32.15 ma

Vp-p (ripple) = 0.00521016 (.meas)


From the above results its quite clear that implementing CM circuit causes Iout to increase which particularly against the aim of the CM circuit. As the CM circuit works by decreasing the load current which according to load POV can be visualised as increase in capacitance.
We can also see the peak to peak ripple voltage in both the circuits, Vp-p for CM circuit should be less than Vp-p ripple of an RC filter, but again the simulations results are quite opposite.

What's wrong here??

CM circuit.png


RC filter.png
 

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Is this not just an extension of your previous thread ?
https://www.physicsforums.com/threads/measuring-ripple-reduction-in-ltspice.1001493/

Why make it so complex ? You have too many places in the circuit to hide difficulties and differences. If the two circuits were merged into one_file.asc, you could compare the results directly.

1. Why specify two voltage sources in series when the DC offset can be specified in one ?

2. What is so special about the detailed 2N4401 model ? Why can you not use a traditional 2N2222 that is included in every version of LTspice ?

3. When 50 Hz is “full wave” rectified, the ripple approximates a saw-tooth with a fundamental frequency of 100 Hz. By specifying a 50 Hz sinewave, you are analysing a frequency component that does not exist, while ignoring every significant harmonic.
 
Because the CM circuit is buffered with the emitter follower, it has a higher output voltage and therefore a higher output current when operating into the same load resistance. The ripple in the CM circuit is also less because load current is not being drawn from the capacitor.

I have given the input waveform a 100 Hz saw-tooth.
Also, offset the DC of the CM voltage in the plot to get better resolution.

schematic-10.jpg

PlotOut-10.jpg
 

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