Measuring ripple reduction in LTSpice

In summary, the capacitance multiplier circuit appears to be ineffective at suppressing ripple, and may even introduce additional noise.
  • #1
228
5
Dear friends,

I am simulating a capacitance multiplier circuit and an RC filter circuit simultaneously. My aim is to check the reduction in ripples when using a cap multiplier circuit against an RC filter.
I am familiar with ltspice but not quite an expert. I am comparing two output waveforms of both the circuits.
Can someone tell me how measure how much ripple has been reduced when cap multiplier is used. How to view that in simulation.??

.asc files have been attached below.

Capture.PNG


Thank you!
 

Attachments

  • capacitance multiplier.asc.txt
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  • RC FILTER STANDLONE.ASC.txt
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  • #2
brainbaby said:
Can someone tell me how measure how much ripple has been reduced when cap multiplier is used. How to view that in simulation.??
I would use the spice .MEASure command. A .MEAS script can count events, trap, and measure points on signals that could be plotted.
Look it up in the help index.

The .MEAS command writes results to the log file.
DO NOT automatically delete the log file at the end of a simulation.
Tools Menu – Control Panel – Operation.
 
  • #3
Baluncore said:
I would use the spice .MEASure command
Probably I have done it.
I got some doubts too.
The peak to peak ripple voltage of RC filter came out to be 0.0046721 and capacitance multiplier is 0.215893 . This shows that ripple voltage of capacitance multiplier is higher than RC filter which make its purpose useless, as cap multiplier is used to suppress ripples.
What seems to be wrong here??

RC filter.PNG

cap1.PNG
 
  • #4
brainbaby said:
This shows that ripple voltage of capacitance multiplier is higher than RC filter which make its purpose useless, as cap multiplier is used to suppress ripples.
I haven't worked with "capacitor multipliers" before, but the bias circuit looks wrong at first glance. Can you provide a link to more information about the operation of the circuit? Thanks.

1617307053856.png
 
  • #5
I'm not familiar with this circuit although after browsing around I'm thinking you might be missing a resistor that should be in parallel with your capacitor; you use it for biasing your transistor to ensure it's in saturation mode.

edit:

Whoops. Acknowledging I made a mistake.
 
Last edited:
  • #6
brainbaby said:
Probably I have done it.
I got some doubts too.
The peak to peak ripple voltage of RC filter came out to be 0.0046721 and capacitance multiplier is 0.215893 . This shows that ripple voltage of capacitance multiplier is higher than RC filter which make its purpose useless, as cap multiplier is used to suppress ripples.
What seems to be wrong here??
If you can compose an appropriate .MEAS script, LTspice will be more than capable of making the measurements. Alternatively you could use the mouse to zoom in on the plot and read out the differential ripple, or turn on the two differential cursors.

To compare two circuits, you might do better placing them on the same schematic.

The efficiency of your attenuator circuits is low. It doesn't appear that your circuits have yet matured to the point where accurate measurements are necessary.

It is not possible to identify or advise circuit changes if the circuit design requirements have not been specified.
 
  • #8
  • #9
Joshy said:
you use it for biasing your transistor to ensure it's in saturation mode.
To bias a transistor either we can increase the base current or base voltage drive i.e more than 0.7 V. I tried with a parallel resistor and found that my base voltage is already above this value (2.44 V and 3.45 with single resistor).
I believe that this much voltage should be sufficient for driving the transistor into saturation??

cap with R2.PNG


single bias resistor.PNG
 
  • #10
Joshy said:
I'm not familiar with this circuit although after browsing around I'm thinking you might be missing a resistor that should be in parallel with your capacitor; you use it for biasing your transistor to ensure it's in saturation mode.
The transistor should not be in saturation.
The lower resistor may not be needed, because it is replaced by the base current.
brainbaby said:
I believe that this much voltage should be sufficient for driving the transistor into saturation??
Saturation occurs when the collector voltage equals the base voltage. Saturation needs to be avoided since the BJT is being operated as an emitter follower.
 
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  • #11
Baluncore said:
Saturation needs to be avoided since the BJT is being operated as an emitter follower.
What I have learned so far is that..in capacitance multiplier circuit the transistor operating in saturation mode acts as a pass transistor passing the current or signal which otherwise would pass through the resistance R1 a component of RC filter.
This causes:
1.signal loss due to voltage drop across this resistor
2.decrease of output voltage (which would be just one diode drop below in the case of when transistor used)
3.shift of corner frequency to upper limit (which would require large impracticable capacitor to compensate for the voltage drop across the resistor and to set the corner frequency as desired)
4. using transistor gives advantage to the circuit to be used in audio applications for higher loads ( high output current or low load resistance).

So these are couple of benefits which can be achieved when transistor is used in saturation whereas the role of emitter follower is quite not clear to me, maybe to negate any loading effect or something like that, not sure.

Please comment!
 
  • #12
brainbaby said:
Please comment!
What do you believe is meant by saturation ?
The collector voltage is in between the base and emitter voltages ?
 
Last edited:
  • #13
Tom.G said:
A decent overview with some details/requirements can be found here:
https://resources.pcb.cadence.com/b...pacitance-multiplier-as-a-power-supply-filter
@Tom.G
According to this article----->" transistor to saturation is important here as this suppresses ripple on the input voltage from changing the output voltage."

the whole idea of cap multiplier circuit is that —-
output current should be as low as possible, which gives an illusion that the value of capacitor is increased in this circuit,(since the slower the discharge of capacitor the more ripple suppression takes place)
however transistor when in saturation results in maximum output current(collector current or minimum voltage drop at CE junction) then —
how can transistor suppress ripple.??
also how the gain of transistor is multiplied with capacitance of the capacitor.?? as stated in some texts.
 
  • #14
Baluncore said:
What do you believe is meant by saturation ?

Base-Emitter voltage VBE > 0.7v
Base-Emitter junction is forward biased
Base-Collector junction is forward biased
Transistor is “fully-ON” ( saturation region)
Max Collector current flows ( IC = Vcc/RL )
VCE = 0 ideal condition
VOUT = VCE = ”0″ output voltage zero
Transistor operates as a “closed switch”
 
  • #15
I just spent a term working on all amplifiers using MOSFETs and so I was all mixed up when I typed this up and said saturation. I did not mean to create that confusion. Whoops!
 
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  • #16
Saturation is simply when Vce is less than Vbe.
During saturation, there can be no base current flowing through the base resistor.

All these so called “capacitance multiplier” circuits that were supposedly used to reduce ripple have become redundant since the advent of the linear regulator. The capacitor is big, with a short life, it is unnecessary, and more costly than a linear regulator IC with a couple of ceramic caps.

If you replaced the capacitor with a zener diode you would improve the performance.
 
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  • #17
For those interested, here is an LTSpice simulation to play with. The AC Voltage source, Diode, and C1 capacitor replace the battery and pulse generator in @brainbaby's original circuit. This is to more closely emulate a transformer-rectifier-filter circuit.

The Voltage, frequency, and R1 R2 were chosen for 'easy' numbers to comprehend in the circuit. (10Vpk at Q1-C, 20mS per AC cycle, and a 3/4 (75%) divider for R1 R2)

Plot traces of interest are the Q1 terminals. The given values yield a 68% ripple across C2, and 28% ripple at the output.

Some things to experiment with: (individually, then in combination!)
Short D1
Change R1 value
Change C2 value
Remove R2
Change C1 value

Green plot trace is Q1-C.
Red trace is Q1-E (load, R3).

Cap-Multi-Draft2 plot.png

Cap-Mult-Draft2 Sch.png

Cheers,
Tom
 

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  • #18
Assuming you're interested from a theoretical PoV rather than practical (when you'd better follow other people's advice), my observations:

The transistor does not look to be in saturation, because the Vce from the data printed at the side is
2.3 V or 3.3 V, both much more than I'd expect in saturation. Also Ie/Ib is 170 or 200, I think high for a saturated transistor whose beta maybe only 100-200 around that current.

Since it is supposed to be (& I think is) operating in active mode, Ve should follow Vb (the clue's in the name - well it is, if you call it an emitter follower rather than a common collector!)

I think Baluncore may be confused in the second sentence here:
Baluncore said:
Saturation is simply when Vce is less than Vbe.
During saturation, there can be no base current flowing through the base resistor.
IMO saturation requires a high base current, though the collector is at a lower potential than the base (NPN).
transistor-tran11.gif

If you look at the green load line here, the transistor would operate linearly with Ib up to about 50 uA, but increasing the base current to 70 to 80 uA would drive it into saturation, with a low Vce sat and Ic independent of further increase in Ib. Reducing Ib would bring it back into the linear range and zero Ib would cut it off.

I can't however see any problem with his suggestion of replacing the capacitor with a zener and I wonder why people would use a capacitor?

I don't understand the Cadence site's reference to using the transistor in saturation, and even less why this should be better. They just state it and give no explanation.
The reference I looked at, https://www.electronics-notes.com/a...transistor/capacitance-multiplier-circuit.php
is no more authoritative and offers little more explanation, but does seem to suggest the transistor is in linear operation.

None of this helps much with your query about LTSpice. Tom's suggestions for experiments sound good. I'd look at Vb to see how much ripple is there. Emitter ripple should, as mentioned before, follow that.
 
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  • #19
Merlin3189 said:
I think Baluncore may be confused in the second sentence here:
Baluncore said:
Saturation is simply when Vce is less than Vbe.
During saturation, there can be no base current flowing through the base resistor.
The CM circuit is unusual in that it has no higher voltage supply to provide collector current for the emitter follower. I was referring specifically to the three component CM circuit where base current must flow through the base resistor, or be drawn from the capacitor charge.

During saturation the base resistor current is reversed, while the capacitor is discharging through the base. The output voltage is therefore falling, following the capacitor discharge voltage downwards.

That implies that while the circuit may be momentarily saturated, it cannot be operating for much time per cycle in saturation. Indeed, the three component CM adjusts it's capacitor voltage, and hence the output voltage, to follow the minimum of the ripple voltage. The time constant of the RC circuit is important here.

Merlin3189 said:
I can't however see any problem with his suggestion of replacing the capacitor with a zener and I wonder why people would use a capacitor?
That is the surprising thing about this circuit. It seems the claim of “capacitance multiplication” is psychologicaly more attractive than is the need to “lower output ripple”.
A zener or linear regulator would win hands down, but not in the unusual case where the ripple and output voltage were variable and completely unspecified.
 
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  • #20
Is it possible this CM circuit has less frequency components in its output compared to clipping or peak detecting with a diode?
 
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  • #21
See attached LTspice files.
By increasing R1 and R2 the the time constant of C2 is lengthened, so C2 has less ripple. That necessitates more gain in the transistor. The R1-R2 divider attenuates the ripple slightly so C2 is charged to below the ripple minimum.
When the ripple is at minimum voltage, C2 is discharged through the base of the emitter follower.
Q1 saturates first, darlington current gain falls momentarily from β2 to β, and the Q2 base current is drawn through the Q1 BE diode from C2.
Zoom in on the output voltage to see a short voltage drop through the Q1 BE diode. Disconnect R2 to make the negative pulse more obvious.
The C2 voltage is therefore tracking the minimum of the ripple.
The output voltage has less ripple, but is the capacitance really being multiplied ?
 

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  • Cap-Mult_4.plt.txt
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  • #22
Baluncore said:
The output voltage has less ripple, but is the capacitance really being multiplied ?
The way to find out is disconnect C2 from the transistor base and connect it either:
1) Parallel with C1
2) Across the load

Then look at the load waveform for each connection.

When done here, C2 has very little effect in either of the alternate connections.
 
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  • #23
Apologies Baluncore, yes it was I who was confused. If the base current is supplied by the capacitor and the collector voltage falls below the base voltage, indeed the current in the resistor must reverse.
 
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1. How do you measure ripple reduction in LTSpice?

To measure ripple reduction in LTSpice, you need to run a simulation of your circuit with and without a ripple reduction circuit. Then, you can use the "AC analysis" tool to plot the output voltage of both simulations and compare the ripple amplitude. The lower the ripple amplitude, the higher the ripple reduction.

2. What is considered a good amount of ripple reduction in LTSpice?

The amount of ripple reduction considered "good" depends on the specific application and the desired level of precision. In general, a reduction of 50% or more is considered good, but it may vary depending on the circuit and its requirements.

3. Can LTSpice accurately simulate the effects of ripple reduction in a real circuit?

LTSpice is a powerful simulation tool that can accurately model the effects of ripple reduction in a real circuit. However, it is important to keep in mind that the simulation results may not always match the real-world performance exactly, as there are many external factors that can affect the circuit's behavior.

4. What are some common techniques for achieving ripple reduction in LTSpice?

Some common techniques for achieving ripple reduction in LTSpice include using capacitors, inductors, and filters to smooth out the output voltage, as well as using feedback and control circuits to regulate the output voltage and minimize ripple.

5. Are there any limitations to measuring ripple reduction in LTSpice?

One limitation of measuring ripple reduction in LTSpice is that the simulation results may not always accurately reflect the real-world performance of a circuit. Additionally, the accuracy of the simulation may be affected by the complexity of the circuit and the accuracy of the component models used.

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