Optimizing Capacitor Selection for BJT with Emitter Degeneration

[likephysics]

A BJT with emitter degeneration resistor reduces gain. To overcome this we can use a bypass capacitor, so the small signal gain is not reduced.
How do you pick this capacitor?
Should it(the capacitive reactance) be less than RE or 1/gm. I don't understand why it should be less than 1/gm.

 

[technician]

The bypass capacitor is in parallel with the emitter resistor Re and should have a reactance, at the lowest frequency you are interested in amplifying, less than the value of Re.
Eg if Re = 1kΩ and the lowest frequency = 500Hz
then 1/(2∏500C) should be less than 1kΩ
this gives C = 31x10^-6 F

 

[likephysics]

The bypass capacitor is in parallel with the emitter resistor Re and should have a reactance, at the lowest frequency you are interested in amplifying, less than the value of Re.
Eg if Re = 1kΩ and the lowest frequency = 500Hz
then 1/(2∏500C) should be less than 1kΩ
this gives C = 31x10^-6 F

That's what I thought. But the book I am referring says it should be less than 1/gm.
See page 225 (example 5.34) of Fundamentals of microelectronics, by razavi
The author also mentions it's a common mistake to make Capacitor less than Re.

 

[skeptic2]

The bypass capacitor is in parallel with the emitter resistor Re and should have a reactance, at the lowest frequency you are interested in amplifying, less than the value of Re.
Eg if Re = 1kΩ and the lowest frequency = 500Hz
then 1/(2∏500C) should be less than 1kΩ
this gives C = 31x10^-6 F

That's what I thought. But the book I am referring says it should be less than 1/gm.
See page 225 (example 5.34) of Fundamentals of microelectronics, by razavi
The author also mentions it's a common mistake to make Capacitor less than Re.

technician, please check your arithmetic. For 1/(2*π*500Hz*1000Ω) I get 0.32uF.

If the Xc is considerably lower than Re, then depending on the peak voltage of your signal and the emitter current you can get into a situation where the amplified signal will be distorted. This is caused by the capacitor being charged through the relatively low resistance of the base-emitter junction but discharging through a potentially higher Re.

If you look at the trace for the voltage across the emitter resistor without the bypass capacitor for a simple sinewave, you will notice that as the voltage passes its peak value, the slope of the curve increases downwards. Compare that with the slope of a capacitive discharge curve in which the slope decreases downwards with time. If there comes a point where the capacitive discharge curve is at a higher voltage than the sinewave, the output will be distorted. I believe this is why the Razavi says the Xc should not be less than Re.

There is another reason I dislike emitter resistor bypass capacitors. As the frequency approaches the lower cutoff frequency, the phase shifts considerably compared to higher frequencies. A configuration I much prefer over this one, series negative feedback, is shunt negative feedback. Shunt negative feed back is achieved with the emitter connected to ground but with a resistor connected between the collector and the base. This arrangement will give you higher gain, more immunity from power supply noise, more constant output level if the supply voltage should change as with a discharging battery and no worry about phase shift or distortion from the bypass capacitor.

 

[technician]

you are absolutely correct skeptic... careless calculator error... display is 3.2 x 10^-7 which I mentally saw as 32 x 10^-6 and of course it is 0.32 x 10^-6

 

[Jony130]

If we looking into emitter from Ce capacitor perspective we see two ways for the current to flow.
First is through Re resistor. And we have the second path through re = 1/gm resistor (I assume that base is grounded).
So as we can see Ce capacitor see two parallel connected resistors Re||re.
In most circuits Re>>re so Rz = Re||re ≈ re.

 

[skeptic2]

If we looking into emitter from Ce capacitor perspective we see two ways for the current to flow.
First is through Re resistor. And we have the second path through re = 1/gm resistor (I assume that base is grounded).

No, the base is not grounded. We are assuming the base has a bias with both base and collector currents flowing through Re. Ce cannot discharge through re because that would reverse bias the b-e junction. Ce's only means of discharge is through Re and if that discharge rate is too slow due to Re >> re, then the b-e voltage may drop below 0.55V and the transistor can go into cutoff.

 

[Jony130]

No, the base is not grounded. We are assuming the base has a bias with both base and collector currents flowing through Re. Ce cannot discharge through re because that would reverse bias the b-e junction. Ce's only means of discharge is through Re and if that discharge rate is too slow due to Re >> re, then the b-e voltage may drop below 0.55V and the transistor can go into cutoff.

Hmm, what can I say. It is obvious that the base is not connect directly to the ground.
I analyzed this "circuit" from small-signal perspective and ignoring the base voltage divider and source resistance and hoe (ro).
And what I'm talking here is a steady state small-signal "time constant" and not transient response.