Pattern Shielding for inductors in Integrated Circuits

  • #1
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I have a bunch of questions on pattern shield for inductors in Integrated Circuits (ICs). Basically, shields are made using thick metals (less resistance) to reduce the coupling to the substrate (which are more lossy generally) in order to improve the Q factor. They are patterned to avoid eddy currents in the shield thereby not reducing the indutance.

1) First, can I view pattern shields similar to Faraday's cage (or shield) blocking EM waves from getting into the substrate? Do EM waves propagate pattern shield through the gaps in between or it's blocked if the wave length is more than the distance of the gaps?
2) What happens to the EM field if it's blocked, does it get lost as heat in the pattern shield or it gets reflected back?
3) Do you necessarily have to ground the pattern shield or it's ok to leave it not connected to anything?

Linked the image
 

Answers and Replies

  • #2
Baluncore
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1) First, can I view pattern shields similar to Faraday's cage (or shield) blocking EM waves from getting into the substrate? Do EM waves propagate pattern shield through the gaps in between or it's blocked if the wave length is more than the distance of the gaps?
It seems to me that the patterned shield is functioning as an electrostatic Faraday screen. It blocks E but not M. The magnetic field still penetrates the substrate. If the fingers are short, measured in wavelengths, they will not resonate, while the magnetic field will flow around and between the fingers.

2) What happens to the EM field if it's blocked, does it get lost as heat in the pattern shield or it gets reflected back?
It will be reflected back by the capacitance of the shield, without the current reversal of a continuous conductive ground plane that cancels inductance. Reactive reflection due to capacitance does not suffer resistive loss.

3) Do you necessarily have to ground the pattern shield or it's ok to leave it not connected to anything?
You need to make the screen in a star pattern without any loops. If the inductor has balanced voltages it should not be necessary to ground the screen, but if the inductor has one end grounded you will need to ground one point on the screen, probably at that point, with pattern radiating away from that point to reduce the maximum length of any finger.
https://upcommons.upc.edu/bitstream/handle/2117/10359/ESSIRC_FS_mmW_benefits_published.pdf

http://smirc.stanford.edu/papers/VLSI97p-cpyue.pdf
 
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  • #3
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Thanks for the reply. That's a great explanation.

1) " It blocks E but not M". Agreed, however, since E and M are related, blocking one of them should attenuate other one as well to some extent right?
2) Why do you say it's reflected back by capacitance? I can understand in a solid ground plane there is total reflection (due to eddy currents), but in a patterned shield it's not intuitive to me. Is it due to the gaps in the pattern shield that creates the capacitance? Can you explain to me in EM domain? You mean to say that the EM waves that get reflected back are not 180 deg out of phase but rather at a different angle?

"It will be reflected back by the capacitance of the shield, without the current reversal of a continuous conductive ground plane that cancels inductance. Reactive reflection due to capacitance does not suffer resistive loss."

3) You mentioned if it's grounded on one-side then I may have to ground pattern shield. What's the reason behind that? Where do you ground it here in this link?
 
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  • #4
davenn
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You need to make the screen in a star pattern without any loops. If the inductor has balanced voltages it should not be necessary to ground the screen, but if the inductor has one end grounded you will need to ground one point on the screen, probably at that point, with pattern radiating away from that point to reduce the maximum length of any finger.
https://upcommons.upc.edu/bitstream/handle/2117/10359/ESSIRC_FS_mmW_benefits_published.pdf

http://smirc.stanford.edu/papers/VLSI97p-cpyue.pdf

Thanks BC ... not a subject I was familiar with, that second link really helped


@iVenky

Thanks for the original Q :smile:
 
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  • #5
Baluncore
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1) " It blocks E but not M". Agreed, however, since E and M are related, blocking one of them should attenuate other one as well to some extent right?
When in space, E and M are related by the intrinsic impedance of free space. When you introduce an electrostatic screen you increase capacitance which lowers impedance. For example, in a transmission line, increasing C lowers the impedance; Z = Sqrt(L/C). The screen changes the impedance of the nearby environment and so can change the ratio of E to M from that in free space.

3) You mentioned if it's grounded on one-side then I may have to ground pattern shield. What's the reason behind that? Where do you ground it here in this link?
Notice that parts of the patterned screen look like a fish skeleton or a feather. There are narrow spines, with combs of isolated parallel lines spreading from the spine. The pattern reduces maximum length of any one conductor line. Your sketch does not show that. It is hard to see unless you look closely in the references that I linked. The fine parallel lines cover the surface best with a pattern at the resolution of the available fabrication process. Fine radial patterns don't cover the surface as completely as do fine parallel lines.

Make the pattern symmetric against the spiral inductor. The aim is to connect points that rise in voltage to points that fall a similar amount in voltage, so capacitive currents are balanced and flow the minimum distance. You do not need to ground the pattern if currents are balanced and static voltage is clamped by PN junctions that prevent insulation breakdown.
 
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Make the pattern symmetric against the spiral inductor. The aim is to connect points that rise in voltage to points that fall a similar amount in voltage, so capacitive currents are balanced and flow the minimum distance. You do not need to ground the pattern if currents are balanced and static voltage is clamped by PN junctions that prevent insulation breakdown.
So you are basically saying there is an ac short in the pattern shield that provides the return path to the EM waves? I think I get the concept now, you are basically adding capacitance in parallel to the inductor that provides the return path to the EM wave and confining it within the shield and doesn't let it go into the substrate. Since no eddy currents are generated, there is no reflection of these EM waves, instead they just return back to the inductor like an LC tank circuit. In other words, there is no loss in energy or flux cancellation thereby increasing the Q factor. However, the self-resonance is now reduced because of the capacitance.

If there is no ac short (as in the case of unbalanced) then you may have to ground the pattern shield otherwise there is no strong path that it may flow through the substrate and return through the substrate, which is lossy.

Is my interpretation right?
 
  • #7
Baluncore
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Is my interpretation right?
I believe you are conflating the LC tank circuit with the external environment of the inductor and the possible environmental energy losses.

No amount of hand waving will explain this to the point where you can draw valid conclusions from reasoning that X causes Y, which causes Z, because Z influences X. There are too many possible confounding parameters, geometries and different language interpretations.
You must take advice from the references as they have modelled the situation. They have made the chips to verify their model is reasonable and sufficiently close to reality.

The first reference I posted, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s” has a useful introduction. I quote part “To reduce energy loss, the inductor's electric field must be terminated before reaching the silicon substrate.

The second reference I posted, “A Comparison Between Grounded and Floating Shield Inductors for mmW VCOs” showed how the screen can be made with a patterned single layer, (from a commercial Design Kit), DK, or from two layers of crossed thin lines as a Floating Screen, FS. See; Fig 3, which shows that the inductor with a FS has higher inductance and higher Q than that with the DK patterned shield.

Now, about grounded or floating …
The FS has lines with a controlled fixed length, so they may be tuned to have transmission line trap characteristics near λ/4. The DK pattern has many different line lengths so it does not have such a critical dimension and can be more broad-band, though sub-optimum at most particular frequencies. If the DK patterned shield is grounded then where and how should that be arranged to best act as a screen? That is dependent partly on bandwidth requirement and the symmetry of field geometry.

Back to the capacitance … The inductor is part of a tank circuit on the chip, with junction capacitance in parallel with the inductor terminals. But this tank circuit is also coupled to it's environment.
Is the inductor track a transmission line over the ground shield, or is it an inductor? I say that it is so short we must model it as a wire inductor.
Are we going to think of the magnetic field passing through the plane of the die as a lone magnetic field, or as an EM wave into the substrate? I say that we are best thinking of the magnetic field alone, we are using the shield to block any electric component, so reducing electrostatic losses into the substrate.

Where a screen, (DK or FS), separates two spiral coils it is only the magnetic flux that couples the primary and secondary windings. The analogy is a wound electrical transformer that has an electrostatic screen between the pri and sec windings. Then the magnetic field couples the windings, but electric fields are blocked from coupling between the windings.
 

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