PCB traces are overheating (due to eddy currents ?)

[Gideon Y]

I managed to overcome the problem. I don't have clear resolution about its root cause, but I found how to eliminate it.

During tests in last weeks (tests for many purposes, not necessary in order to resolve PCB heating) I paid attention that heating of PCB and capacitors strongly linked to amplitude of ripple - i.e. voltage level decrease on capacitors due to discharge during half of clock cycle. There are several factors affecting ripple amplitude, including load current, step capacitance and clock cycle period. No matter what of these parameters changed, if it resulted in ripple amplitude increase, it proportionally increased power dissipation. There can be several explanations for that relationship, eddy currents is just one of them.
I therefore performed frequency scan, and it quickly became evident that system behaves much better at higher frequencies. At clock rate higher than 100 KHz PCB stays cold, as well as as all other components.

The most surprising outcome is that total efficiency raised. It is counter-intuitive. My basic assumption is that almost every system is loosing energy on transitions, due to dielectric and magnetic effects. So more transitions per second means more energy lose.
I don't understand exactly why increase of clock rate has resolved everything so easily.
But presently there is no longer an issue with strange heating of PCB.

Thank you very much for your help !

Gideon

 

[Baluncore]

I doubt that (without heavy simulation) it would be possible to modify trace routing to prevent hot spots created by current loops.

You do not need simulation. You just need to avoid laying it out to look like the schematic circuit.

Run wide tracks like transmission lines, one on top, the counter current below. Split the capacitor patches into two parts, separate on each side of the counter-twisted t'line axis, so the t'line alternates between sides of PCB.

Put diodes along both outside edges of the line, rather than between separate lines of capacitors. That is quite different to the way the circuit diagram is drawn.

Each diode is placed in the top track of a short hairpin line, made from two tracks, one above the other and connected at a patch of thru vias.

Where two diodes are in parallel, keep their adjacent traces separate for as far as convenient, so track resistance can improve balance of diode current. Indeed, your pairs of parallel diodes might be separated onto opposite sides of the line, to service separate sides of the capacitor lines.

LTspice model with layout sketch.

Questions;
1. Is it driven by a square wave from a half? or from a full H-bridge? Voltage?

2. What is the value of the input inductors you were using while it was overheating at 50 kHz? Inductance of input wires will become more important as you raise the frequency.

3. What is the value of your individual capacitors, about 2uF for 50 kHz? That can be halved at 100 kHz to 1 uF.

4. How did you decide the taper variation of capacitance used along the cascade; 80, 40, 27, 20, 16, 14, 12, 10, 9, 8, 8, 7. Do you have a rule for optimum values, or a reference to the analysis?

 

[Gideon Y]

Thank you for useful insights. I will implement them in the next version.

Answers to your questions:

(1) Square wave from full H bridge, 45*2 = 90V p-p

(2) Inductors are not installed, ignore them. They were designated to handle a problem which currently doesn't exists.

(3) In past I used 22uF ceramic capacitors, now I'm using 4.7 uF. In future I will further decrease capacitor values or (preferably) will decrease amount of capacitors per step.
I'm aware that at higher frequency it is possible to use smaller capacitors. Please note however that maximum current allowed per capacitor is lower for smaller capacitors, so there is a limiting factor other than C*F

(4) I reviewed several published methods to select capacitance per step, but eventually decided to use rule of my own: capacitance should be proportional to the current flowing through the step. If you think the rule is incorrect please let me know.