- #1
sabine_
- 4
- 0
Hi all,
I would like to deposit a thin titanium film (d=100nm) with pvd sputtering on an epoxy encapsulated
IC-chip to protect the chip against corrosive gases.
Titanium target (diameter: 100mm) is straight above IC-Chip (length and width: 6mm, height:2mm), working pressure ~ 1E-4 mbar.
My question is:
What film thickness can I expect at the sidewall (height dimension) of the chip ?
perfect step coverage: ~100 nm or bad step coverage: ~ 0 nm ?
Thanks
Best regards
Sabbi
I would like to deposit a thin titanium film (d=100nm) with pvd sputtering on an epoxy encapsulated
IC-chip to protect the chip against corrosive gases.
Titanium target (diameter: 100mm) is straight above IC-Chip (length and width: 6mm, height:2mm), working pressure ~ 1E-4 mbar.
My question is:
What film thickness can I expect at the sidewall (height dimension) of the chip ?
perfect step coverage: ~100 nm or bad step coverage: ~ 0 nm ?
Thanks
Best regards
Sabbi