PVD sputtering - step coverage

[sabine_]

Hi all,

I would like to deposit a thin titanium film (d=100nm) with pvd sputtering on an epoxy encapsulated
IC-chip to protect the chip against corrosive gases.
Titanium target (diameter: 100mm) is straight above IC-Chip (length and width: 6mm, height:2mm), working pressure ~ 1E-4 mbar.
My question is:
What film thickness can I expect at the sidewall (height dimension) of the chip ?
perfect step coverage: ~100 nm or bad step coverage: ~ 0 nm ?

Thanks
Best regards

Sabbi

 

[Daz]

I guess it depends on the distance from the sputter head to the sample. In general sputtering is quite directional so I’d expect very poor coverage on the sidewalls, unless you’re using a planetary drive sample holder.