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Homework Help: Syntax Issues With Verilogger Pro (2001,2005 syntax to 1995 syntax)

  1. Apr 14, 2010 #1
    I have the following example that I need to compile in using Verilogger Pro. The example is that of a 4-bit universal shift register. We are told to take the code from our text book and create a test bench. I am not worried about test bench at this time, I am having problems compiling the code. The code given to us is in 2001,2005 syntax. Our compiler will only work in 1995 syntax. I have narrowed down the errors to one line, but knowing how the program works, it could be anywhere, I cannot find it. I have mailed my TA about this almost 2 days ago and have not gotten a response.

    My question is where is the error in my code?

    Code (Text):
    module Shift_Register_4_str (A_par, I_par, s1, s0, MSB_in, LSB_in, CLK, Clear);
    output [3:0] A_par;
    input [3:0] I_par;
    input s1, s0, MSB_in, LSB_in, CLK, Clear;
    assign [1:0] select = {s1,s0};
    stage ST0 (A_par[0], A_par[1], LSB_in, I_par[0], A_par[0], select, CLK, Clear);
    stage ST1 (A_par[1], A_par[2], A_par[0], I_par[1], A_par[1], select, CLK, Clear);
    stage ST2 (A_par[2], A_par[3], A_par[1], I_par[2], A_par[2], select, CLK, Clear);
    stage ST3 (A_par[3], MSB_in, A_par[2], I_par[3], A_par[3], select, CLK, Clear);

    module stage (i0, i1, i2, i3, Q, select, CLK, Clr);
    input i0, i1, i2, i3;
    output Q;
    input [1:0] select;
    input CLK, Clr;
    wire mux_out;
    Mux_4_x_1 M0 (mux_out, i0, i1, i2, i3, select);
    D_flip_flop M1 (Q, mux_out, CLK, Clr);

    module Mux_4_x_1 (mux_out, i0, i1, i2, i3, select);
    output mux_out;
    input i0, i1, i2, i3;
    input [1:0] select;
    reg mux_out;
    always @ (select or i0 or i1 or i2 or i3)
    case (select)
    2'b00: mux_out = i0;
    2'b01: mux_out = i1;
    2'b10: mux_out = i2;
    2'b11: mux_out = i3;

    module D_flip_flop (Q, D, CLK, Clr);
    output Q;
    input D, CLK, Clr;
    reg Q;

    always @ (posedge CLK or negedge Clr)
    if(~Clr)Q<=1'b0; else Q<=D;
    Below is my error log:

    Code (Text):
    C:\Users\Muta\Desktop\HDL3\3-1b.v: L5: error: parse error, unexpected '[', expecting error or IDENTIFIER or HIERARCHY_IDENTIFIER or '{'
    C:\Users\Muta\Desktop\HDL3\3-1b.v: L5: error: 'select' not declared
    Any ideas as to where the error is?
  2. jcsd
  3. Apr 14, 2010 #2


    Staff: Mentor

    Your error log seems to identify line 5 as the culprit, as it is not expecting the expression in brackets.
    Code (Text):
    assign [1:0] select = {s1,s0};
    Do you have any documentation for the 1995 version of Verilogger Pro? If so, does the syntax allow for bracketed expressions after an assign statement?

    I don't pretend to have any knowledge whatsoever of Verilogger Pro syntax, but this is where I would start.
  4. Apr 14, 2010 #3
    Unfortunately, I have no documentation for that version. Our textbook brushes the topic of Verilog, lord knows why I am learning it, but it mixes both syntaxes. One minute we are reading 1995 syntax, and the next we are reading 2001, 2005.

    I actually figured it out after playing around with the code long enough:

    Code (Text):

    module Shift_Register_4_str (A_par, I_par, s1, s0, MSB_in, LSB_in, CLK, Clear, select);
    I acutally had to initialize it in the first line of the module. Funny thing is that my initial post was how the textbook had it, so I was on my own for figuring out the errors. This really isn't the greatest textbook to learning this software.
  5. Apr 14, 2010 #4
    Okay, I can compile it, but I had to get ride of the [1:0] after the Assign statement. So my waveforms aren't coming out correct. They aren't doing what they are supposed to be doing.
  6. Apr 15, 2010 #5
    It's probably simplest to tell VeriLogger's GUI to use the new VeriLogger Extreme simulator instead of VeriLogger Pro. VeriLogger Extreme is Verilog 2001 compliant (and mostly 2005 as well). If you have an old version of VeriLogger that doesn't have Extreme, you can download a more recent one from:

  7. Apr 15, 2010 #6
    Thing is that my copy is an evaluation version from my textbook. Won't I have to pay?
  8. Apr 15, 2010 #7
    No, you don't have to pay. The one on the web site is just a newer version of the one included in the book. Also, SynaptiCAD is actually giving away full 6-month trial licenses (which enables the stuff not turned on in the book version).
  9. Apr 16, 2010 #8
    Unfortunately, that copy of Verilogger doesn't help me. I tried my code and it didn't work.
  10. Apr 16, 2010 #9
    Yep, there's an error in the code. But the error reported by VeriLogger Extreme was fairly clear about the problem I think. Try making the following code change:

    wire [1:0] select = {s1,s0};
  11. Apr 18, 2010 #10
    Tried that and still not working.
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