Need help verilog code error

[rosesun]

Need urgent help ...verilog code error

Hello ,
I am new to verilog ...can someone help me urgent ..
I have a task for 8 bit register where in i have to model hierarchial modeling ...
here are my modules ... correct me please

Someone please patietnly go through all modules and let me know whas wrong in it ...


`timescale 1ns/1ns
module register(reg_out,data,ena,clk,rst);

output [7:0] reg_out;
input [7:0] data;
input ena,clk,rst;

regmux register0(reg_out[0],q,data[0],ena,clk,rst);
regmux register1(reg_out[1],q,data[1],ena,clk,rst);
regmux register2(reg_out[2],q,data[2],ena,clk,rst);
regmux register3(reg_out[3],q,data[3],ena,clk,rst);
regmux register4(reg_out[4],q,data[4],ena,clk,rst);
regmux register5(reg_out[5],q,data[5],ena,clk,rst);
regmux register6(reg_out[6],q,data[6],ena,clk,rst);
regmux register7(reg_out[7],q,data[7],ena,clk,rst);

endmodule


`timescale 1ns/1ns

module regmux(r,q,d,ena,clk,rst);

output r;
input q,d,ena,clk,rst;
wire x,qb;
MUX2to1 muxinst(x,q,d,ena);
dff dffinst(q,qb,rst,clk,x);
endmodule



`timescale 1ns/1ns

module MUX2to1(x,q,data,enable);

output x;
input q,data,enable;
wire q1,data1,enablebar;

not (enablebar,enable);
and (q1,q,enablebar);
and (data1,data,enable);
or (x,data1,q1);
endmodule
~


`timescale 1ns/1ns

module dff(q,qb,clear,clock,data);
output q,qb;
input clock,data,clear;
wire cb,clr,clkb,clk,db,d,s,sb,r,rb;

defparam SR1.x=4.8,SR2.x=4.5,SR3.x=5;
defparam SR1.y=3.3,SR2.y=4.5,SR3.y=4.5;

not #(2.3) not1(cb,clear);
not #(2.Cool not2(clr,cb);
not #(2.3) not3(clkb,clock);
not #(2.5) not4(clk,clkb);
not #(2.3) not5(db,data);
not #(2.3) not6(d,db);

SR_Latch2 SR1(s,sb,clr,clk,1'b1,rb);
SR_Latch2 SR2(r,rb,clk,s,d,clr);
SR_Latch2 SR3(q,qb,1'b1,s,clr,r);

endmodule

~

`timescale 1ns/1ns

module SR_Latch2(Q,Qb,s0,s1,r0,r1);

output Q,Qb;
input s0,s1,r0,r1;

parameter x=4.5;
parameter y=4.5;

nand #(x) nand1(Q,s0,s1,Qb);
nand #(y) nand2(Qb,r0,r1,Q);

endmodule





i am getting tthis error ...ncvlog: *E,EXPMPA (regmux.v,21|0): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 0
ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
..

Therre is error regmux module ..but seems to be evrything perfect ...can someone help ... Also i doubt there is soehting wrong with parameter overriding ..also need helo in it ,,,,,

Thanks
Rose

 

[anorlunda]

It looks fine to me also. Are you sure that you are compiling the right file? The one you show in the post?