Understanding Dead Time Compensations in Electric Machine Drives

[mohammadmaaz789]

TL;DR

cannot understand this deadtime compensation method from:
Control of Electric Machine Drive Systems Book by Seung-Ki Sul chapter 7.1.1

https://i.stack.imgur.com/hSOU2.png
https://i.stack.imgur.com/wE2Iy.png
https://i.stack.imgur.com/R7FKK.png

cannot understand this deadtime compensation method. So I have provided the whole cut out of the section of this book.
BOOK: Control of Electric Machine Drive Systems Book by Seung-Ki Sul chapter 7.1.1

The Problem I have is that in figure 7.1 the author says to make the +gate and the -gate to turn on without dead time in 7.1a off sequence and 7.1b ON sequence.

I mean it basically means shorting if I do that, and I think that is the sole purpose of having dead time in the first place.

 

[DaveE]

I'm not sure I understand your confusion here. As long as you don't turn on both the high and low side transistors at the same time, you won't short out the buss. The diode polarity won't allow current to flow from the + power supply to the - power supply if only one transistor is on. If a transistor turns on, the opposing diode will turn off (commutate). If all of the transistors are off, one of the diodes will turn on to allow current flow during the dead time. If you have any dead time without those diodes, you'll get a big voltage spike from the load inductance that will probably break something.

If that doesn't make sense please ask you question with a bit more detail.

PS: There will be a short period (hopefully!) when a transistor turns on but can't carry the entire load current when both the transistor and diode are conducting. But during this time the current through the transistor is limited and won't act like a short across the buss. But since the diode is on, the entire buss voltage will be across the transistor while it's current is increasing. This high power dissipation period is the dominant form of switching losses in the transistor, normally referred to as turn on losses. The transistor voltage can't fall into saturation until it has enough base/gate drive to carry the entire load current and allow the diode to turn off. This is all assuming an inductive load, of course.

There can also be some short circuit current across the buss during this transition during the time it takes the diode to turn off. These are the reasons you need fast semiconductor switches to operate at higher frequencies, or high efficiencies.

 

[mohammadmaaz789]

I'm not sure I understand your confusion here. As long as you don't turn on both the high and low side transistors at the same time, you won't short out the buss. The diode polarity won't allow current to flow from the + power supply to the - power supply if only one transistor is on. If a transistor turns on, the opposing diode will turn off (commutate). If all of the transistors are off, one of the diodes will turn on to allow current flow during the dead time. If you have any dead time without those diodes, you'll get a big voltage spike from the load inductance that will probably break something.

If that doesn't make sense please ask you question with a bit more detail.

PS: There will be a short period (hopefully!) when a transistor turns on but can't carry the entire load current when both the transistor and diode are conducting. But during this time the current through the transistor is limited and won't act like a short across the buss. But since the diode is on, the entire buss voltage will be across the transistor while it's current is increasing. This high power dissipation period is the dominant form of switching losses in the transistor, normally referred to as turn on losses. The transistor voltage can't fall into saturation until it has enough base/gate drive to carry the entire load current and allow the diode to turn off. This is all assuming an inductive load, of course.

There can also be some short circuit current across the buss during this transition during the time it takes the diode to turn off. These are the reasons you need fast semiconductor switches to operate at higher frequencies, or high efficiencies.

The first 2 complementary gating signals(red) are mentioned in the book(so I am taking it as an example to explain my point ) (i>0 OFF sequence)

The red ones are the assumed wave forms

where in actuality the bottom would be the case so there will be a chance for shortage right?

So i said before this is why we add deadtime so that the turning on of one doesn't coincide with the other.

In this method of compensation as far as i can understand he says for 2 out of the 4 cases in the book The author says: To remove Tdead and just put Tset = Torg in the following two cases... maybe?

So i am just worried while applying it to my hardware system it would short the dc source.

 

[DaveE]

Sorry, I'm not sure I understand his compensation scheme from the photos provided. It sounds like he (correctly) doesn't allow both transistors to be on at the same time, which is required. Transistor drive circuits nearly always have some delay until the base/gate drive gets into the active region. So I guess he's advancing the timing of the drive signals to compensate for that? That's OK provided that you don't ever get both devices on at the same time.

I'm also a bit confused about what's wrong with a little dead time. You have the diodes to allow a current path at that time. Is there a reason that you don't want the diodes to conduct? Are they too slow in turning off? Maybe you need very high duty cycle? Why do you care about "dead time compensation"?

Anyway, you will need to understand the details of your application and how the devices should be switched, then design the drive circuit to achieve that. Following someone else's procedure without understanding the details is risky.

Personally, I find this much easier to understand for inductive loads if you focus first on the transistor/diode currents and then determine the device voltages that result from the circuit. But either perspective works in the end.

 

[mohammadmaaz789]

Sorry, I'm not sure I understand his compensation scheme from the photos provided. It sounds like he (correctly) doesn't allow both transistors to be on at the same time, which is required. Transistor drive circuits nearly always have some delay until the base/gate drive gets into the active region. So I guess he's advancing the timing of the drive signals to compensate for that? That's OK provided that you don't ever get both devices on at the same time.

I'm also a bit confused about what's wrong with a little dead time. You have the diodes to allow a current path at that time. Is there a reason that you don't want the diodes to conduct? Are they too slow in turning off? Maybe you need very high duty cycle? Why do you care about "dead time compensation"?

Anyway, you will need to understand the details of your application and how the devices should be switched, then design the drive circuit to achieve that. Following someone else's procedure without understanding the details is risky.

Personally, I find this much easier to understand for inductive loads if you focus first on the transistor/diode currents and then determine the device voltages that result from the circuit. But either perspective works in the end.

Yes i think I need to search elsewhere now.
My aim was regarding common mode voltage and dead time effects its so that's the reason i wanted to learn about compensation of deadtime.

 

[DaveE]

Yes i think I need to search elsewhere now.
My aim was regarding common mode voltage and dead time effects its so that's the reason i wanted to learn about compensation of deadtime.

It isn't uncommon in some switching power supply controllers to measure things like DC offsets in the AC waveforms generated and adjust the switch timing via a feedback loop to eliminate them. I've mostly seen that in power supply primary side switching with transformers to avoid saturating the core due to imbalance in the + and - drive waveforms. This is almost always a slow adjustment. There are many approaches to this.

 

[Dullard]

The most expensive case of a dead-time error that I've ever seen:

The (analog) electronics used to 'point' GPS Block II spacecraft solar panels used a 'nulling' diode pair (mounted on the panel) to maintain the panels 'normal' to the Sun. That (slow) signal was used to drive an H-Bridge which ran the Panel drive motors. It worked great. Note that the signal from the null sensor is fed through 'slip rings' in order to get from the panel to the drive electronics. For Block IIA, there was a requirement to improve 'rad hardness.' Part of that involved larding a lot of filtering (inductors, capacitors...) all over the place, but there were no (intentional) changes to the drive system.

The combination of slip-ring 'noise' (brief discontinuity) and all of that new reactance meant that the (formerly) slow sensor signal could change polarity very quickly and very often (while the drive was running / slip-rings bouncing). Drives were failing on orbit (blowing fuses). I don't recall that they entirely lost any spacecraft (redundancies), but (for the several that were already on-orbit) the panels had to be manually 'pointed' several times a day for the remaining life (10 years, or so) of those vehicles.

A fold-back current limiter was added to the motor drive power feed all remaining IIA vehicles.