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What are the gains of having a smaller fabrication process?

  1. Feb 5, 2009 #1
    What are the advantages of having a smaller die fab process on a CPU or GPU? Doesn't it reduce heat production and power consumption?
     
  2. jcsd
  3. Feb 5, 2009 #2

    turbo

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    Getting the on-chip components smaller means that the processes carried on within the chip can be carried on faster, and it also means that you can pack a lot more computing power into a given piece of silicon real-estate. The smaller electrical paths are more resistive than larger ones, and so more of the power is lost as heat, and as you populate chips more densely, the amount of waste heat increases. Add to this the propensity to clock the chips at higher and higher speeds, and the heat problem magnifies. Heat is a major factor in chip development.
     
  4. Feb 5, 2009 #3

    mgb_phys

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    Money - fabs charge per area of silicon.
    If you half the linear size you can put 4x as many components in the same area.
    Because of edge,kerf losses and failure effects the cost actually goes something like feature size2.5 - 3.5
     
  5. Feb 5, 2009 #4

    turbo

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    I wonder if chip-designers can manage to factor in enough redundancy to accommodate localized failures and reduce reject-rates that way.... just a thought.
     
  6. Feb 5, 2009 #5

    turbo

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    Smart, chip-born rerouting around damaged or error-prone areas could save a lot of losses due to rejects.
     
  7. Feb 5, 2009 #6

    mgb_phys

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    They used to, it was a big research field, self diagnosing chips with multiple instruction paths that could route around damage. Most of the aim was to make rad hard chips for military and space. You also had CCDs that came with a rom listing all the bad pixels so you could map them out.
    In the end production yields went up to the point where it wasn't really worth it - since most of the cost of a bad chip is testing there isn't really an advantage in a chip that can repair itself because you have already wasted so much money detecting it. It's better to put the research into not having a bad one in the first place.

    The other big improvement with small chips is the area failure rate. when you had 3-4 inch wafers and large chips you might only have 5-10 chips on a wafer, so any single bad spot cost you 10-20% of the yeild. With 12in wafers and tiny chips you might have several hundred chips, so a single point failure now costs you <1%
     
  8. Feb 5, 2009 #7

    berkeman

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    "Smaller die fab process" is not a standard way of asking this question. Just to clarify, the fab is the physical facility that has one or more fab lines. Each line will use a process, and support one or more geometries (the sizes of the transistors and other components on the die). The size of each die is determined by the size of the process, and how many components are on each die (the complexity).

    So I think you are asking "What are the advantages of smaller geometries on integrated circuits? Why would a smaller geometry be used on a CPU?" Something like that? If so, turbo and mgb have covered the considerations pretty well. Here's more info if you're interested:

    http://en.wikipedia.org/wiki/Integrated_circuit
     
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