What is in all in a Makefile?

  • Thread starter Eus
  • Start date
In summary, the conversation discusses the use of "::" in "all::" in a Makefile and the difference between single-colon and double-colon rules. Double-colon rules allow for multiple rules for the same target and are executed independently of each other. These rules are useful in cases where the method used to update a target depends on which prerequisite files caused the update. It is also mentioned that double-colon rules are not commonly used and an implicit rule will be used if no commands are specified.
  • #1
Eus
94
0
What is "::" in "all::" in a Makefile?

Hi Ho!

Executing GNU Make:

If Makefile only contains the following lines,

Code:
all:
	echo $@

it will produce

Code:
echo all
all

If Makefile only contains the following lines,

Code:
all::
	echo $@

it will still produce

Code:
echo all
all

But, if Makefile only contains the following lines,

Code:
all:::
	echo $@

it will produce

Code:
Makefile:1: *** missing target pattern.  Stop.

all: is just the usual way. all::: is an error.
all:: is the mystery that I don't know.

I know, all:| exists for order-only execution.
But, all:: is not documented in GNU Make texinfo.

Does any of you know what the use of all:: is?

Thank you.


Eus
 
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  • #2
I think it is being intepreted as "all:" followed by an empty target "blank:"
but "all:::" would have 2 targets "blank:" targets the same.
 
  • #3
all: is an ordinary (i.e., single-colon) rule. You can have only one 'all:' rule in a makefile (exception: you can have multiple dependency-only rules for the same target). all:: is a double-colon rule. You can have as many of these as you want in a makefile, but you cannot mix ordinary and double-colon rules.

'man make' doesn't say much. Use 'info make' instead. This is the make.info section on double-colon rules (type 'info make double-colon' on the UNIX command line):
info make double-colon said:
Double-Colon Rules

"Double-colon" rules are rules written with `::' instead of `:'
after the target names. They are handled differently from ordinary
rules when the same target appears in more than one rule.

When a target appears in multiple rules, all the rules must be the
same type: all ordinary, or all double-colon. If they are
double-colon, each of them is independent of the others. Each
double-colon rule's commands are executed if the target is older than
any prerequisites of that rule. If there are no prerequisites for that
rule, its commands are always executed (even if the target already
exists). This can result in executing none, any, or all of the
double-colon rules.

Double-colon rules with the same target are in fact completely
separate from one another. Each double-colon rule is processed
individually, just as rules with different targets are processed.

The double-colon rules for a target are executed in the order they
appear in the makefile. However, the cases where double-colon rules
really make sense are those where the order of executing the commands
would not matter.

Double-colon rules are somewhat obscure and not often very useful;
they provide a mechanism for cases in which the method used to update a
target differs depending on which prerequisite files caused the update,
and such cases are rare.

Each double-colon rule should specify commands; if it does not, an
implicit rule will be used if one applies. *Note Using Implicit Rules:
Implicit Rules.
 
Last edited:
  • #4
D H said:
'man make' doesn't say much. Use 'info make' instead. This is the make.info section on double-colon rules (type 'info make double-colon' on the UNIX command line):

Yes, you are right! Thank you very much for telling me that it is called double-colon rule and it is documented in the texinfo file.


Eus
 

1. What is a Makefile?

A Makefile is a file that contains instructions for a computer program to build and compile source code into an executable file or library.

2. What does a Makefile contain?

A Makefile typically contains a set of rules that specify the dependencies between source code files, as well as the commands needed to build and compile the code.

3. How do you use a Makefile?

To use a Makefile, you need to have the make utility installed on your computer. Then, you can simply run the make command in the directory where the Makefile is located, and the make utility will execute the instructions in the Makefile to build and compile the source code.

4. What are the benefits of using a Makefile?

A Makefile allows for automated building and compiling of source code, which can save time and reduce errors. It also helps to manage complex projects with multiple source code files and dependencies.

5. Can a Makefile be used for any programming language?

Yes, a Makefile can be used for any programming language as long as the compiler and other necessary tools are available and can be called through the make utility.

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