Why does the top surface of a Silicon Die measure close to 0 ohms?

[austinuni]

I have gotten access to a large bare silicon die (almost 1" across, 14nm process) that my company gets from a fab. I've been monkeying around with an ohmmeter placed at the top of the die, with the test leads placed at various points around the die, and I almost always measure the same value (0.2 ohm) as when the leads are touching together directly. At one point I measured 18 ohms with the leads about 1/8" away from each other on the die. On the back side of the die, I always get a reading consistent with non-conduction.

I understand that the top layer of the die is a passivity layer designed to protect the die, and I assume this top layer is non-conductive, but perhaps it is not present in the silicon die that I have. (I think this die may have been a test reject, otherwise I probably would not have it).

I measured the resistance of the top layer of a completed silicon wafer from a different device (much smaller die), and between the test points on the same die, I either get a non-conductive reading or a very small reading like around 20 ohms.

I think below the passivity layer of the die would be the metal layers, and I assume that's what the test leads are touching. But why is it always close to 0 ohms? Wouldn't I get a non-zero conductive reading or inconsistent reading between non-zero conductive and non-conductive, reflecting the various paths through the transistor circuit that is conducting the meter's current?

 

[berkeman]

Are you sure you are measuring the top of that die and not the bottom side? As you say, the top of die are passivated. The bottom of a die will generally be conductive to mate up with a center ground pad for good device grounding and sometimes for heat conduction out of the package.

 

[austinuni]

I can see the patterning of the circuit on the "top" side of the die. I have 5 of these bare silicon dies, and they all measure the same way. I almost always get a 0.2 ohm reading, and then sometimes a reading of 20 ohms or so.

I wonder if it has something to do with the probability that they are test rejects? Like maybe the top metal layers were constructed totally wrong?

 

[berkeman]

I would think that even wafer sort test rejects would have passivation on top. Is there a chance that these were destined for "FIB" (focused ion beam) rework to test a fix to the mask? Depending on whether the FIB rework is a cut or a jump (via deposition), they may need to remove the top passivation layer to be able to do the FIB...

https://en.wikipedia.org/wiki/Focused_ion_beam

 

[austinuni]

I suppose it is possible these were destined for FIB, but I don't have much background on these die.

Is it possible that the test leads are punching through all the metal and silicon layers to some "base" layer, even though I am holding them gently? Each time I touch the die with the leads, it appears to make a small scratch/dent in the die.

edit: I tried much narrower probes and a much lighter touch, and still get the same result.

 

[f95toli]

There can be many different explanations.
Note that most silicone that is used for fab is doped. This can be on purpose (because you need n or p doped Si to make devices) but even "natural" Si if quite conductive because of impurities.
High-resistive Si is quite expensive and even then it is usually "compensated" (they add p or n dopants to compensate naturally occurring impurities). "intrinsic"high-ohmic Si is available,but way more expensive that standard Si so it only really used for e.g. high frequency applications.

Also, sometimes you can see a change in conductivity depending on the light level; that is the conductance increases (Resistance drops) if you shine a light at the wafer.