Why is W=0 not included in the excitation table for counters?

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Sinister
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Hi guys.

I'm wondering if someone could explain why when trying to make a 3 bit up/down counter using T flip flops, there are two and gates connected to the final multiplexer ?

Can someone explain how you approach this?

And same with the JK Flip flop but with an xor gate.

I'm really confused on how you come up with this.

Thanks.
 
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When doing a Google search on "3 bit up/down counter using T flip flops" it appears to be a homework problem. May I suggest you Google search those many sites and find your answers there?
 
When we are doing the excitation table for counters...why is the W=0 for the next state not included?