Recent content by es1

Your intuition is likely right but your terminology is wrong. What I suspect you're thinking is if I place a computer in one cold room and a (well designed) space heater in another, turn them both on, return in 30 minutes, then the room with the computer will have a lower ambient temp rise...

Just express the currents in terms of the node voltages. No KVL needed. See section III, nodal analysis, step 3 in this link below. http://www.mit.edu/~godoy/6098/study/review1_analysis.pdf

Is this true? Do you have an example of a circuit that requires KVL to be solved? I totally agree when solving circuits by hand using both can save a lot of work and time but I didn't think using both was strictly required. I ask because I was under the impression spice only uses KCL when...

I am not going to do the math but I will forward you to this article. http://www.magnet.fsu.edu/education/tutorials/magnetacademy/operations/fullarticle.html This lab builds 20T to 45T magnets and they claim their weakest DC field magnet takes 17MW. 25T is a very serious magnet.

Is it working in lab or in spice? When you say you want very low offset, what do you mean? The resistor biasing scheme used might be a problem depending on what "low" means (these days when someone says they want a low offset I think sub 1mV. But you are using a 3mV nominal opamp so...)...

Nevermind, I just realized it would get cleaned up on the next cycle around. So it is different in the sense that the oscillation doesn't persist.

Does this work? If phase of the S and R falling edge equals the mismatch then you're back into the same situation, no? It seems like the external rule imposed on the driving circuit of "don't let S and R falling edges be within the time of the worst case possible mismatch" is the only thing...

This is a known problem with the ideal SR latch with perfectly matched gates. If the gates have any mismatch in delay, like a real latch will, then the circuit will find a stable state. The only problem is, you don't necessarily know which gate is slower. So like the old joke goes, if it...

Multimeter's themselves are pretty robust beasts. But I can say with certainty that is due to the fuses within them. I've replaced a good number of fuses in the Fluke over the years. Every "damaged" DMM I've ever seen was recovered by a fuse change.

btw, i found this via a google when looking for the v vs i of a light bulb over this voltage range. here the bulb's large signal behavior isn't ohmic so it can't be modeled accurately over this range with an equation of the form y=mx+b. you'll see all that, and an explanation, in the results...

See part 2 in this link. It describes exactly your experiment, even uses your method of force voltage with batteries, and how to plot out the v vs i curve and what not. http://teachers.usd497.org/agleue/unit_pdfs/electricity_unit_1/electricity_unit_1_ohm_laws_and_light_bulb_lab.pdf

A standing wave is not a traveling wave kinda by definition. But the voltage, at a non-zero, point should be changing with time and this function will have a dependence on frequency. For example, see this illustration: http://www.youtube.com/watch?v=3BN5-JSsu_4&feature=related

I think the load is floating (well, 1Gohm anyway) relative to the feedback network. Try adding a ground on R1.

Lostmind, Do you have the actual CAD of the layout or just the image? Can the CAD tool just print a connection report on all the nets and a BOM? Should be fairly straight forward to reconstruct a schematic from that information.

I have to admit I didn't really follow the logic but maybe this will help: You have to also consider what lowered Vc to saturate the NPN. For the standard NPN common emitter what you should find is if the biasing network is holding Ib constant then Ic will have to drop, i.e. the collector...