Recent content by stn0091

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    Engineering PSPICE - simulation of CMOS astable circuit

    The output plots? Alright. I'm assuming you mean the capacitor voltage when you say Vcc. V(1) is VDD = 5 V, V(2) is Vi and Vcc (same node), V(3) is the output of the first inverter, V(4) is the output of the second inverter.
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    Engineering PSPICE - simulation of CMOS astable circuit

    Homework Statement I'm trying to simulate the following circuit in OrCAD PSPICE. Homework Equations The Attempt at a Solution * 8.20 Vdd 1 0 5V MP1 3 2 1 1 PMOD MN1 3 2 0 0 NMOD MP2 4 3 1 1 PMOD MN2 4 3 0 0 NMOD R1 3 2 1000 C1 2 4 1uF .MODEL...
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    Engineering Circuit Analysis of a Positive Offset Clamping Diode Circuit

    Not exactly a triangle wave, but it still follows the same general shape. Top/pink is Vo, middle/purple is Vs, bottom/red is Vc.
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    Engineering Circuit Analysis of a Positive Offset Clamping Diode Circuit

    Yes, I simulated the circuit using PSPICE. Just from observation of the circuit, I can tell how it behaves for the first few cycles, even without the simulation. I just can't manage to write it down with some work. At 0 seconds, is the circuit assumed to be in DC steady state? Is it valid...
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    Engineering Circuit Analysis of a Positive Offset Clamping Diode Circuit

    Homework Statement Plot the waveforms for capacitor voltage VC, output voltage Vo, and diode voltage Vd given that Vs is a 20 Vpp triangle wave with period T. Use CVD model with diode VON = 0.7 V. Homework Equations KVLs? The Attempt at a Solution From my basic...
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