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Circuit Analysis of a Positive Offset Clamping Diode Circuit 
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#1
Oct2112, 01:03 AM

P: 7

1. The problem statement, all variables and given/known data
Plot the waveforms for capacitor voltage V_{C}, output voltage V_{o}, and diode voltage V_{d} given that V_{s} is a 20 V_{pp} triangle wave with period T. Use CVD model with diode V_{ON} = 0.7 V. 2. Relevant equations KVLs? 3. The attempt at a solution From my basic understanding of a clamper, I can see that the output is offset by +2 V. Thus Vo begins at +2v, Vc begins at 2V, and the diode voltage begins at 0V and heads towards 10V (off, reverse bias). However, I can't manage to show this analytically. KVL around the left side gives: V_{s}  V_{c} + V_{d}  2V = 0 At the same time, I know that V_{o} + V_{d}  2 = 0. I can't really solve anything with just these two equations though. I can say that V_{s } V_{c} = V_{o}, but these equations just take me in circles. Again, I understand that Vo starts at 2V and rises in step with Vs. With that said, Vo = 12 V at when Vs reaches its first 10V peak. At T/2 when the input becomes negative, the diode turns on and the capacitor can start charging. With the diode on, output Vo is clamped to 2V  0.7V = 1.3V. The 0.7V is the diode drop from the CVD model. It stays on until 3T/4. By that point, the capacitor has charged to 11.3V. From 3T/4 onwards, diode remains off. Capacitor has no discharge path and remains at 11.3V. At the second 10V peak, Vo is 21.3V. I just don't know how to show ANY of that with work, which doesn't earn me any points when I have to analyze this on a test. 


#2
Oct2112, 08:11 AM

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P: 5,245

Hi stn0091.
Do you have simulation software that you can construct this and see precisely what it does? It helps a lot when you know what you are aiming to explain. There can be a big difference between how a circuit behaves for the first so many cycles, and how it operates well down the track once it has settled down to a steady state. 


#3
Oct2112, 02:06 PM

P: 7

Yes, I simulated the circuit using PSPICE. Just from observation of the circuit, I can tell how it behaves for the first few cycles, even without the simulation. I just can't manage to write it down with some work.
At 0 seconds, is the circuit assumed to be in DC steady state? Is it valid if I say the entire circuit is assumed to have been off for a long period of time such that the capacitor is discharged and open and there is no current anywhere in the circuit? If that's the case, that might help a bit. Under DCSS at 0^{}: V_{s} = 0V V_{c} = V_{s}  V_{o} V_{o} = V_{d} + 2 There is no current, so there's no drop across the diode so V_{d} = 0V. Working back up that list up equations, V_{o} = 2V V_{c} = 2V Those numbers agree with my intuitive understanding of the circuit and what PSPICE says. Question: I said that the capacitor was fully discharged at DCSS for t = 0^{}. How can V_{c} = 2V in that case? Shouldn't it be zero? Or does "discharged" just mean any value < 0? This stuff from basic circuits is really throwing me off. That was all at DCSS at 0^{} seconds. Now turn V_{s} on. Diode will be in reverse bias so the circuit is still "off." With KVL, I again have: V_{s}  V_{c}  V_{o} = 0 Capacitor has no path so V_{c} remains constant at 2V. Let's say I'm at the first 10V peak at T/4 seconds. 10  (2)  V_{o} = 0 V_{o} = 12V Is that all logically sound so far? Are my assumptions valid? 


#4
Oct2112, 06:57 PM

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P: 5,245

Circuit Analysis of a Positive Offset Clamping Diode Circuit
We need your graph of v₀(t). 


#5
Oct2212, 02:25 AM

P: 7

Not exactly a triangle wave, but it still follows the same general shape. Top/pink is V_{o}, middle/purple is V_{s}, bottom/red is V_{c}.



#6
Oct2212, 05:51 AM

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Are those waveforms close to what you expected to find? Can you explain what they show, and some of their features?



#7
Apr2413, 12:12 AM

P: 8

This is a clamper circuit.When the input is at its negative peak,the diode is on and the capacitor is charged opposite to what is shown in the circuit.The capacitor is charged to V=20+20.7=21.3V.
Now when the input is at its positive peak,the diode is off and the capacitor stays at the same charged voltage. The output in first case is (20.7)V=1.3V.Voltage across diode is 0.7V The output in second case is 21.3+10=31.3V.Across diode is also 31.3V since open circuit. The output is never negative. 


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