Bizarre Behavior in Discrete PMOS

AI Thread Summary
The discussion revolves around the unexpected delay in the PMOS i_D vs V_ds/V_sd curve for the CD4007 MOSFET IC, contrasting it with the NMOS curve, which behaves as anticipated. The difference in performance is attributed to the inherent mobility of electrons versus holes, with electrons exhibiting higher mobility, leading to greater conductivity in NMOS transistors. Concerns are raised about the PMOS curve remaining at zero until a specific threshold, which is not as clear as in NMOS behavior. The conversation also touches on the need for sufficient V_gs to prevent simultaneous conduction in both PMOS and NMOS devices. The presence of a small resistor in the NMOS measurement setup is noted, which affects the interpretation of the current readings.
Apogee
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Some of my colleagues and I captured the i_D vs V_ds/V_sd curves for the CD4007 MOSFET IC (http://www.ti.com/lit/ds/symlink/cd4007ub.pdf). We did this for the NMOS and PMOS transistors. I have attached the curves to this post. The NMOS curve is as expected. However, the PMOS curve seems to be delayed by a few volts. Does anyone happen to know why the PMOS curve would have such a delay?

NMOS curve: https://raw.githubusercontent.com/Roman-Parise/Circuits-Lab/master/Spring2017/Lab2/data/nmos.png

PMOS curve: https://raw.githubusercontent.com/Roman-Parise/Circuits-Lab/master/Spring2017/Lab2/data/pmos.png
 
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The NMOS transistor operation is based on the mobility of Electrons in the Source-Drain channel.
The PMOS transistor operation is based on the mobility of Holes in the Source-Drain channel.

The mobility of Electrons is much higher than that of Holes. That translates to higher conductivity as shown in the differing slopes of the graphs you supplied.
If you want to get into the details, look at the formulae on pg 202, and the graph on pg 203 (PDF pgs 8, 9) in:
https://people.eecs.berkeley.edu/~hu/Chenming-Hu_ch6.pdf

Hope it helps.
Tom
 
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As I recall in CMOS circuits to achieve symmetry the PMOS FET has to be twice the size of the NMOS.
 
I understand these concepts, but I'm more concerned with the fact that the Id vs Vsd curve remains zero until a certain point. For Id vs Vsg, this makes sense, since there's a threshold voltage. But this doesn't make sense to me for Id vs Vsd.
 
For PMOS you show I(mA) against Vsd.
For the NMOS you show Vr(mv) vagainst Vds.
How can we compare different plots?

It may be that since devices are operated with their P and N gates tied, there needs to be sufficient Vgs to prevent heavy conduction by both P and N at the same time.
 
Baluncore said:
For PMOS you show I(mA) against Vsd.
For the NMOS you show Vr(mv) vagainst Vds.
How can we compare different plots?

It may be that since devices are operated with their P and N gates tied, there needs to be sufficient Vgs to prevent heavy conduction by both P and N at the same time.

I apologize for the confusion. A small resistor was placed in series with drain (about 100 οhms) when measuring the NMOSs drain current. Vr is the voltage drop over that resistor. So id is essentially proportional to that curve.
 
Apogee said:
A small resistor was placed in series with drain (about 100 οhms) when measuring the NMOSs drain current. Vr is the voltage drop over that resistor. So id is essentially proportional to that curve.

Might not be related to your question but that means the current range for the NMOS FET was roughly 0 to 0.9mA and for the PMOS it was 0 to 350mA?
 
Apogee said:
I'm more concerned with the fact that the Id vs Vsd curve remains zero until a certain point.

Almost as if there is a diode in the path somewhere.
 

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