Realizing 8K x 8 Memory Module: ROM/RAM Addressing

[Colours123]

Question:

An 8K x 8 memory module consists of 2K x 8 of ROM which starts from address 1000H and 6K x 8 of RAM which starts from address 2000H. The module is to be realized using 2K x 8 RAM devices and 2K x 8 ROM devices. The RAM devices have active low write enable (WE) and active low chip enable (CE) inputs, while the ROM devices have active low chip enable (CE) inputs. The address decoding is to be done exhaustively.

(a) How many different SRAM and ROM memory devices are needed to realize the memory module?
(b) Draw a memory map of the memory module using hexadecimal notation. Show clearly the memory ranges occupied by the different memory devices in (a).I could not tally the number of addresses required for the memory module. It required 1 2K x 8 ROM and 3 2K x 8 RAM. 2K x 8 ROM/RAM needs 11 address line and another 2 more address lines for the input of the decoder, 4 more address lines for the address starting from 2000H. Then, wouldn't it be a total of 17 address lines and that exceeds 16 address lines?

I am not sure if I interpret it correctly, please show me guidance to the question. Thank you.

 

[berkeman]

Question:

An 8K x 8 memory module consists of 2K x 8 of ROM which starts from address 1000H and 6K x 8 of RAM which starts from address 2000H. The module is to be realized using 2K x 8 RAM devices and 2K x 8 ROM devices. The RAM devices have active low write enable (WE) and active low chip enable (CE) inputs, while the ROM devices have active low chip enable (CE) inputs. The address decoding is to be done exhaustively.

(a) How many different SRAM and ROM memory devices are needed to realize the memory module?
(b) Draw a memory map of the memory module using hexadecimal notation. Show clearly the memory ranges occupied by the different memory devices in (a).I could not tally the number of addresses required for the memory module. It required 1 2K x 8 ROM and 3 2K x 8 RAM. 2K x 8 ROM/RAM needs 11 address line and another 2 more address lines for the input of the decoder, 4 more address lines for the address starting from 2000H. Then, wouldn't it be a total of 17 address lines and that exceeds 16 address lines?

I am not sure if I interpret it correctly, please show me guidance to the question. Thank you.

You use the same address lines for the decoder as for the memory address bus, so that does not add extra lines. Can you show us the address map?

 

[Colours123]

You use the same address lines for the decoder as for the memory address bus, so that does not add extra lines. Can you show us the address map?

I am not sure if it is this way but I do not have enough address to select the chips.