I'm having trouble with the following VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity circuit is
port (a, b, c: in std_logic;
f1, f2, f3, f4, f5, f6: out std_logic);
end circuit;
architecture...