Recent content by hoheiho

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    [verilog] change from always@ to assign

    Did anyone can see what's the problem :(?
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    [verilog] change from always@ to assign

    Homework Statement Halo, I have written a always@ (code i,pic1) which can output what I want but the result is delayed 1 clock cycle, therefore I have changed it to assign (code ii,pic2)and try to output the recover signal immediately when pcreg_1 is changed. But waveform is not what I wanted...
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    Optimizing Soft Error Pulse Width for CPU Fault Injection

    Thanks for your reply I am using a simply processor and run it in modelsim using verilog. I want to find out the soft error rate and do the recovery. Before the recovery stage, I need to see which block in the processor cause the most errors rate and then consider how much recovery blocks...
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    Optimizing Soft Error Pulse Width for CPU Fault Injection

    Homework Statement Hi, I am trying to inject some faults into a CPU manually. But I am not sure what should the soft error (SET) pulse width should be? I know that is different in different case. Therefore, I am going to set up a random generator to generator the SET pulse width. But what range...
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    Verilog - generate random delay time in testbench

    Sorry for the typing error again :(. When I do the simulation, the code doesn't work what I prefer. I think I need to use two for loop together to change the MAX and MIN value. I am trying to fix it now. Thanks :)
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    Verilog - generate random delay time in testbench

    Thank for your reply Sorry for my poor english, I didnt get what you mean by wait #1ns? I would like to create a for loop and get the random delay timing between 0 ns to 300ns. It will generate a random delay time each 30ns. (i=0;i<300;i=i+30). For example 0 ns to 30ns: j = 20ns -> inject value...
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    Verilog - generate random delay time in testbench

    Homework Statement Hi, I would like to generate a random delay time and value in testbench. This is what I did: for(i=0;i<300;i=i+30) begin j = i + {$random} % (300 - i) // MIN + {$random} % (MAX - MIN ) #j b = {$random} %3; #3ns b = 3'b000; end I want to generate random...
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    Synthesis using synopsys design compiler

    Homework Statement Hi, I am trying to complie my counter (writen in system verilog) using synopsys design compiler. It comes out this error: The expression in the reset condition of the 'if' statement in this 'always' block can only be a simple identifier or its negation. (ELAB-303) ***...
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    Counter from 0 to 11 then back to 0 (system verilog)

    sorry, 1 more question can i use count to the counting?not i. like if count < 12 ... .. i have try that in my code but it doesn't work. is that becuase count is the output so i cannot use it for internal counting?
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    Counter from 0 to 11 then back to 0 (system verilog)

    ready is the input, if the ready=0 and last for 3 clock cycle, it will count from 0 to 2.
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    Counter from 0 to 11 then back to 0 (system verilog)

    Thanks for your reply what does RST mean?
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    Counter from 0 to 11 then back to 0 (system verilog)

    Hi all, i am trying to do a counter using system verilog. The counter will count from 0 to 11 then back to 0 and start the counting again. Input = rdy, if rdy = 0, start counting. Output = count I have done the simulation for my code and it is not working as i prefer. It will...
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    How can I compare bits and perform bit shifts in SystemVerilog?

    thanks for the help i know how to work it out now
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    How can I compare bits and perform bit shifts in SystemVerilog?

    I can use 3 stages to hold 3 bit and do the compare. And this is what i did before like A = 0 0 1 S1 = 0, S2 = 0, S3 = 1. If i do this i got around 300 stages after because there are some more bit i need to compare after. Now my idea is use A to hold 1 digital (001). And compare the input with...
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    How can I compare bits and perform bit shifts in SystemVerilog?

    thanks for the reply sorry for i didnt say it clear again I have to return to the starting part immediately when the bitmatch is 0. For example: A = 011 B = 001 0 compare with 0 (i) ---> bitmatch=1 1 compare with 0 ---> bitmatch=0 Now compare the last bit of A which is 1 to the first bit of B...