Verilog - generate random delay time in testbench

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hoheiho
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Homework Statement


Hi, I would like to generate a random delay time and value in testbench. This is what I did:

Code:
for(i=0;i<300;i=i+30)
  begin
  j = i + {$random} % (300 - i) // MIN + {$random} % (MAX - MIN )
  #j b = {$random} %3;
  #3ns b = 3'b000;
  end

I want to generate random value in random time. int i give me the range of random time. j is the actual random delay timing and b is the random value.
What I want to do here is generate a range -> generate delay time-> use value b in the the generated delay time -> recover value b after 3ns.

But it comes out error with:
**near "#": syntax error, unexpected '#', expecting ';'

Is that mean I can only use a actual value for the delay? Like #30, #20...but not a unknown value #j ? I have google it but cannot find any useful information about my problem..

Thank you very much for the help
Ivan
 
Last edited:
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Thank for your reply
Sorry for my poor english, I didnt get what you mean by wait #1ns? I would like to create a for loop and get the random delay timing between 0 ns to 300ns. It will generate a random delay time each 30ns. (i=0;i<300;i=i+30).
For example
0 ns to 30ns:
j = 20ns -> inject value b at time 20ns -> recovery back to b = 3'b000 at time 23ns -> start next for loop cycle ->
30ns to 60ns:
...
..
.
 
Sorry for the typing error again :(.

When I do the simulation, the code doesn't work what I prefer. I think I need to use two for loop together to change the MAX and MIN value. I am trying to fix it now.

Thanks :)