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Homework Help: Synthesis using synopsys design compiler

  1. Apr 6, 2012 #1
    1. The problem statement, all variables and given/known data
    Hi, I am trying to complie my counter (writen in system verilog) using synopsys design compiler. It comes out this error:

    The expression in the reset condition of the 'if' statement in this 'always' block can only be a simple identifier or its negation. (ELAB-303)
    *** Presto compilation terminated with 1 errors. ***

    What factor may care this problem? what can i try to do?

    Thank for the help
  2. jcsd
  3. Apr 6, 2012 #2


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    Staff: Mentor

    Perhaps you should post the code for your "always" block so we can see your error? :wink:
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