[verilog] change from always@ to assign

[hoheiho]

Homework Statement

Halo, I have written a always@ (code i,pic1) which can output what I want but the result is delayed 1 clock cycle, therefore I have changed it to assign (code ii,pic2)and try to output the recover signal immediately when pcreg_1 is changed. But waveform is not what I wanted. Did I miss somethings in (code ii)? The recover is high in 2 clock cycle and I cannot get 0.

code i

always @(posedge clk)
begin
  if (store)
      if (m2==pcreg_1)
        recover = 0;
      else
        recover = 1;
  else
      if (m1==pcreg_1)
        recover = 0;
      else
        recover = 1;     
end

code ii

assign recover = (store && (m2==pcreg_1))? 1'b0:1'b1;
assign recover = (!store && (m1==pcreg_1))? 1'b0:1'b1;

Could anyone give me a hand for me :(?

Thank you very much for help
Ivan

 

[hoheiho]

Did anyone can see what's the problem :(?