Recent content by mmcc2014

  1. M

    Mitigating Capacitive Coupling in FPGA Demo Board with Membrane Keypad

    Thanks for that solution, I will give it a shot tomorrow and let you know if it resolved it.
  2. M

    Mitigating Capacitive Coupling in FPGA Demo Board with Membrane Keypad

    Both actually, I'm not doing anything fancy. Initially, I thought the high frequency may be playing a role.
  3. M

    Mitigating Capacitive Coupling in FPGA Demo Board with Membrane Keypad

    The I/O standard is 3.3-V LVTTL and your assumption about the method employed is correct. Does the solution remain the same? Is there any way to predict this type of behaviour or standard formulas? Would changing the current strength or I/O standard help at all?
  4. M

    Mitigating Capacitive Coupling in FPGA Demo Board with Membrane Keypad

    I have an FPGA demo board and on the GPIO I have attached a 4 x 3 membrane keypad. This keypad is simple, create a current on the column pins and look for a completed circuit on the row pins. http://ebay.arduinodiy.co.uk/ebayimages/ebaycontent/kppinout2.jpg...
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