I don't think I'm understanding the requirements correctly.
When does Z output 1? It reads as if Z outputs 1 when X & Y are 1, but then why do I need 4 states / 4 modulus?
How many flip-flops do I need based on the following requirement? I'm thinking 2 flip-flop since each flip-flop can be a 0 or 1. So each flip-flop holds 2 states.
Design a clocked synchronous state machine with two inputs, X and Y, and one output, Z. The output should be 1 if the number of 1...
He said looking at my K-map that I can wrap the entire row 2 but can't cancel out C and D. He's reasoning is that they're more than 2 bits apart. Only adjacent cells can be canceled.
He then had me draw 7 circles to wrap the 1's in the map. Somehow his analysis ended up with me having 2 XOR...
If there's 4 inputs to the circuit but one input "C" is not inplemented at all in the circuit, how does the circuit process inputs from "C"?
I verified via the truth table that even without the C input the results are still correct. I guess the input for C is not part of the input or output...
The professor have talked about the K map. The chapter I'm working on have not discussed it officially yet. It'll be the next chapter.
I'm wondering if I'll be forced to not use the K map to solve a problem on an exam. Don't know if they only care as long as the solution is correct or that...
Figured it out. Man this is long.
From the second solution
A'C' + A (BC + BC' + B'C')
A'C' + A (B (C+C') + B'C')
A'C' + A ( B + B'C' )
A'C' + A ( (B + B') (B + C') )
A'C' + A ( B + C' )
A'C' + AB + AC'
C' (A' + A) + AB
C' + AB
I wonder is it always a trial and error process in...
Reduce the following to 3 literals
A'C' + ABC + AC'
C'(A'+A) + ABC
C' + ABC
or
A'C' + ABC + AC'
A'C' + A(BC + C')
A'C' + A(BC + C'(B + B'))
A'C' + A(BC + BC' + B'C'))
I can't go any further. What am I doing wrong?
The book has the answer as AB + C'