Thanks for your help
I have finished part of them,but I met one problem when I write VHDL to test code s5
Here is my code and the error message( I used Quartus II version 7.0 to synthesis):
for s5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use...
Hello, everyone!Now I'm studying VHDL, and our teacher gave us some questions as follows:
1. Complete the following code fragment and try to synthesize the VHDL:
process begin
wait until Clk = '1';
Phase <= "0" after 0 ns; Phase <= "1" after 10 ns;
end process;
What is the error message...