# Boolean expressions for larger MOSFET circuits

1. Jun 30, 2010

### jegues

1. The problem statement, all variables and given/known data
See figure.

2. Relevant equations

3. The attempt at a solution

I tried breaking the circuit down into a bunch of small logic gates but I'm having a tough time putting things back together into one big circuit. (One boolean expression)

So far I've determined that the left-most part of the circuit is a NAND gate and the right-most part is a NOR gate.

I'm still not to sure how C comes into play, but I tried to determine when exactly C is accessed. (See figure)

Is there an efficient (preferably somewhat systematic) way of solving these types of problems?

Any help/tips/suggestions would be greatly appreciated!

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2. Jun 30, 2010

### Zryn

I believe you are meant to write a truth table of sorts to see which gates being on or off contribute to the final outcome of Z. Interestingly though there is a gate just below Z which is not labelled. Is it prudent to assume that that gate is always on?

*Nevermind, I see D & E control whether that gate is on ... needs more coffee!

*Can you show your reasoning for saying the right-most part of the circuit (D & E) is a NOR gate?

Last edited: Jun 30, 2010
3. Jul 1, 2010

### jegues

Since I have 5 variables to deal with, if I were to start writing truthtable for this circuit I'd end up with,

$$2^{5} = 32$$

32 possible outcomes.

Doesn't this seem a bit tedious for solving a problem like this? There has to be an easier way.

Because if you do a truth table solely for that portion of the circuit the output (in red, see figure) will always be zero unless both gates (D & E) are off.

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4. Jul 1, 2010

### Zryn

Yes, a 5 variable truth table would be a bit tiresome, but it would be very systematic!

Alternatively, since you know how the NOR gate works, perhaps you could combine D & E into one gate, calling it Y for example. Then you would have only 4 variables to deal with, and 16 is much easier than 32.

Actually, are there any other area's where you could combine the function of two gates into one gate, calling it X for example? If there were, you would only have 3 variables to deal with, and 8 is even easier than 16!

5. Jul 1, 2010

### vela

Staff Emeritus
The pull-up resistor will cause the output to be high unless an appropriate combination of FETs is on. For example, in the NOR gate, the output is high unless D or E is on. For the complex gate on the left, what combinations of inputs will create a path to ground and allow the output to be pulled low?

6. Jul 2, 2010

### jegues

If A, B and C are high then the output will be pulled low, but I have another question.

You mentioned a pull up resistor,

Where is this and does it do?

Also, back to the original question, now that I know which FET combinations set the input low, how do I create a boolean expression from this?

7. Jul 2, 2010

### vela

Staff Emeritus
That's one possible path. There's another one as well.
It's RL. It causes the output of a gate to be high unless the right combination of inputs is on. Without the right combination of inputs, there's no path to ground, no current through the resistor, and therefore, by Ohm's law, no voltage drop across the resistor; hence, the output of the gate will be VS. If there is a path to ground, the output will be pulled to low.
Going back to the NOR gate, the output is 1 unless D or E is on. The statement in bold describes a NOR gate, right? The condition D or E results in an output of 0.

For the complex gate, you've identified one possible way for the output to be 0: A and B and C are on. Consequently, there will be a term not (A and B and C). Now, you just need to figure out what the other part of the gate corresponds to.

8. Jul 4, 2010

### jegues

The only other combination I can see that will pull the output low is if D and E are low and C is high.

With everything said, it's still pretty fustrating trying to write a boolean expression to describe this large circuit. It's simple to write a boolean expression for each seperate section.

I've identified a NOR and a NAND gate and the cases in which the output is pulled low. What else is left? How can I turn all this information into my final answer?

9. Jul 4, 2010

### vela

Staff Emeritus
Well, you don't really have a NAND gate, which may be confusing you. That structure is part of the complex gate.

Let's call the output of the NOR gate F. So you've figured out that Z will be low if A, B, and C are all high or if F and C are both high. Algebraically, you'd say

Z = not ((A and B and C) or (F and C))

Does that make sense?

10. Jul 4, 2010

### Zryn

Here is an alternative (and more systematic) way than looking at the circuit and using experience to analyse it, using the information you already know.

The trick would be analysing all 32 combinations (5 gates) so you can get to the point where you can look and realise you might only need to do 8 combinations (3 gates) or even merely translate the gate on/off combinations you can see into the equation directly.

You won't be able to do that unless you do the hard yards and become familiar with how it all comes together.

Also, when you get the boolean equation have a go at simplifying it. You should be able to look at the final equation and understand and have it make sense, as this example is very neat.

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