Calculating Gain of a Multistage Amplifier

[erece]

Homework Statement

for the circuit shown , if i want to calculate gain of the second stage then do i need to consider the output resistance of first stage as the source resistance for the second stage ?

Homework Equations

The Attempt at a Solution

first stage is common collector and second is common base
and voltage gain for common base is

Av = (gm/RS)(RcllRL)(re ll RE ll RS)

If yes then the output resistance of first stage (Common collector) will be
RO1 = re ll RE ll ro = .02513 KΩ
RS = Ro1
then gain equation will become AV2 = gm2(RC)(re2llRS) = 76.92
but in the solutions they have ignored the effect of RS and used AV2 = gm2(RC)
i.e they ignored the effect of stage 1 on stage 2 to find Vo2/Vo1 but have considered the effect of stage 2 on stage 1 to find Vo1/Vi
please clarify this

 

[aralbrec]

i.e they ignored the effect of stage 1 on stage 2 to find Vo2/Vo1 but have considered the effect of stage 2 on stage 1 to find Vo1/Vi

Do you mean Rin2 was computed and used to find Vo1/Vi ?

 

[erece]

Do you mean Rin2 was computed and used to find Vo1/Vi ?

yes.

 

[aralbrec]

You've modeled the second stage as a resistor of Rin2. With Rin2 in place, you found Vo1/Vi. This means you can put the second stage in Rin2's place and Vo1 will *still* be given by the same Vo1/Vi.

When you've calculated Vo1/Vi this way, you are not ignoring the effect of stage2 on stage1; Rin2 models this effect.
(A potentially confusing question you may want to ask your professor is why you only modeled stage 2 with an input resistance rather than a resistance plus a thevenin voltage as thevenin's theorem requires. You are right to ignore it if you assume signals only travel in one direction -- ie the output cannot affect the input).

 

[erece]

(A potentially confusing question you may want to ask your professor is why you only modeled stage 2 with an input resistance rather than a resistance plus a thevenin voltage as thevenin's theorem requires. You are right to ignore it if you assume signals only travel in one direction -- ie the output cannot affect the input).

if i need to model the second stage as thevenin voltage plus thevenin resistance then i need to remove the first stage to calculate Vth, but second stage does not have any independent source so Vth should be 0
am i right ??

 

[erece]

sorry
in the first post i did some mistake. In that i wrote the formula for voltage gain of common base as Av = (gm/RS)(RcllRL)(re ll RE ll RS)
and for my circuit the second stage is common base for which RE is ∞ and no RL . So gain expression will become Av = (gm2/RS)(Rc)(re ll RS)
i forgot to divide by Rs. But still answer in the textbook for gain of second stage is 153.8 and the factor of 2 is coming because they ignored Rs.
This is a question from electronic circuits analysis & analysis by donald neamen

 

[aralbrec]

but second stage does not have any independent source so Vth should be 0
am i right ??

Yes. But the thevenin model can complicate quickly even if there are no independent sources. This happens when some fraction of the output is fed back toward the input (suppose you attached a feedback resistor from the output back to the input). The thevenin model is still valid but the equations become very nasty. It's preferable to think of those sorts of circuits in terms of feedback where we model the circuit differently to isolate the feedback elements. You will see this later on.

sorry
in the first post i did some mistake. In that i wrote the formula for voltage gain of common base as Av = (gm/RS)(RcllRL)(re ll RE ll RS)
and for my circuit the second stage is common base for which RE is ∞ and no RL . So gain expression will become Av = (gm2/RS)(Rc)(re ll RS)
i forgot to divide by Rs. But still answer in the textbook for gain of second stage is 153.8 and the factor of 2 is coming because they ignored Rs.
This is a question from electronic circuits analysis & analysis by donald neamen

I don't know what circuit your general formula is associated with but what you came up with having re || Rs isn't right. Rs, if it were to be used, would be in series with re because the source feeds into the emitter in series.

Ignore Rs, just look at the second stage and apply an input. Insert a low-freq small signal model for the transistor into the circuit. I stuck a T-model in there but it turns out to be just as easy with a hybrid-pi model.

My diagram for the second stage is attached and appears on the left side with the emitter, base and collector of the transistor marked EBC. Sorry for the bad drawing, I have next to no sw on my netbook. The arrows may go in a different direction than you are used to because the transistor is pnp rather than the more commonly studied npn. With a pnp, a higher voltage at the emitter wrt to the base causes current to flow into the transistor and out of the collector.

Vo is just the voltage across Rc: Vo = α i_e Rc. And i_e is the current into the emitter = Vi / r_e. So Vo/Vi = α Rc / r_e. Since α = g_m r_e, Vo/Vi = g_m Rc

Note this result agrees with the provided solution A₂ = gm2 Rc

(Optional: I will just insert an asterisk here and point out that there is little current gain through a common base transistor, ie almost the same amount of current flows into the emitter as comes out of the collector. This observation is important when cascode amplifiers are studied. Cascode has a common emitter amplifier to do voltage gain (appearing as an output current) and then the current from that is fed through a common base transistor, which does not modify the output current. It does, however, increase the output resistance of the combination greatly and if you model the overall cascode as a Norton equivalent -- current source in parallel with output resistance -- you will see high gains are possible).Next, no, Rs from stage 1 should not show up in the formula. This is because your gain from the first stage includes the input resistance of stage 2 already.

If you had taken scissors and cut the circuit between stage 1 and stage 2, you would have to model stage 1 as a thevinin source in series with Rs and then attach that to stage 2 to complete the analysis.

Instead you have not cut the circuit, but have model stage 2 as a thevenin resistance and found the voltage entering stage 2 from stage 1 with this resistance in place. This transfer function has *already* taken into account the load of stage 2 on stage 1.

The right side of the diagram shows the difference.

In the top right diagram, we have cut the circuit so we model stage 1 as a source in series with Rs, which we will use to drive stage 2 (represented by Ri2) to complete the analysis.

In the bottom right diagram, we kept stage 2 in the circuit. Stage 1 is modeled as a source and Rs as before but now we are analyzing the circuit with Ri2 in place. This is what is done in this problem so the v2/v1 we find already includes the effect of loading on stage 1.

I don't know if that helps to clarify?