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Confused on Gate Delays, what would the wave form look like?

  1. Oct 20, 2006 #1
    Hello everyone,
    I'm lost on how to interpret wave forms in VHDL given a certian logical gate. For example:
    If I have 2 nand gates, that look like this:
    https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/nand-nand.bmp?1703 [Broken]

    And the question is the following:
    For a nand-nand gate shown below, if the values of inputs 'a', 'b', and 'c' are originally 0, 1, 0, respectively, and later changed to 1, 1, 1,
    which waveform shows the correct behavior of this nand-nand gate (assume each nand gate has a gate delay as 1ns)?

    Well if you plug in the intial values a, b, and c the t0 will be 1, and y will also be 1

    After 1ns, a, b, and c change, so
    y = 1, and t0 = 0

    Now none of the waveforms displayed look like the one i drew...
    t0 is going to go from 1 to 0 after 1 ns
    but the output value y isn't going to change at all, its 1 in both cases, so I would think it would be a straight line...but here are the choices i have:

    a: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-4.bmp?9380 [Broken]

    https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-3.bmp?7232 [Broken]

    https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-1.bmp?6865 [Broken]

    https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-2.bmp?3563 [Broken]

    I my drawing looks closest to c or d, but i also noticed c and d are the exact same image arn't they? i'm confused, any help explaining how gate delays affect wave forms would be great or an explanation of what hte answer would be. thank you.
    Last edited by a moderator: May 2, 2017
  2. jcsd
  3. Oct 20, 2006 #2


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    Two of the possible answers look the same.:confused:

    You should eliminate the ones that fail based on what you have stated about T0.
    Then state your considerations of delay time in relation to the remaining choices.
  4. Oct 21, 2006 #3
    i know a and b are wrong... but c and d are both wrong too, y is never changing, its always 1 that is what is confusing me, perhaps there is an error?
  5. Oct 22, 2006 #4


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    Why do you think Y will always be 1?
    I would generally disagree with that.
    Try doing your timing diagram showing the states of all 4 inputs. Note that T0 is an input and will not change state in sync with inputs a c.

    In this problem it looks like any setup time is being ignored. So you might get different results, in a simulator or real world circuit, than the answer expected here. Although, timing issues like this are common and cause a lot of headaches if you're not paying attention.
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