Hello everyone, I'm lost on how to interpret wave forms in VHDL given a certian logical gate. For example: If I have 2 nand gates, that look like this: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/nand-nand.bmp?1703 [Broken] And the question is the following: For a nand-nand gate shown below, if the values of inputs 'a', 'b', and 'c' are originally 0, 1, 0, respectively, and later changed to 1, 1, 1, which waveform shows the correct behavior of this nand-nand gate (assume each nand gate has a gate delay as 1ns)? Well if you plug in the intial values a, b, and c the t0 will be 1, and y will also be 1 After 1ns, a, b, and c change, so y = 1, and t0 = 0 Now none of the waveforms displayed look like the one i drew... t0 is going to go from 1 to 0 after 1 ns but the output value y isn't going to change at all, its 1 in both cases, so I would think it would be a straight line...but here are the choices i have: a: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-4.bmp?9380 [Broken] b: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-3.bmp?7232 [Broken] c: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-1.bmp?6865 [Broken] d: https://cms.psu.edu/AngelUploads/Content/MRG-060818-113032-mji/_assoc/EB238A71723B494FBF1CC149443E7B49/q2-2.bmp?3563 [Broken] I my drawing looks closest to c or d, but i also noticed c and d are the exact same image arn't they? i'm confused, any help explaining how gate delays affect wave forms would be great or an explanation of what hte answer would be. thank you.