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Decrement with J-K FF and gate/gates

  1. Oct 15, 2011 #1
    Last edited by a moderator: May 5, 2017
  2. jcsd
  3. Oct 15, 2011 #2

    LCKurtz

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    It looks like the J and K inputs on the LSB are connected together and connected to one of the AND inputs. But nothing is connected to them as an input. Also the i input is missing. Is that your missing input? I know, I know, the answer is yes, and with that change your circuit is logically fine.

    But the standard way of displaying flip-flops and gates is with the inputs on the left and the outputs on the right. Look at your circuit in a mirror and it would be properly displayed.
     
  4. Oct 15, 2011 #3
    what about now?
    http://img35.imageshack.us/img35/3654/20111015001.th.jpg [Broken]
     
    Last edited by a moderator: May 5, 2017
  5. Oct 15, 2011 #4

    LCKurtz

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    Much better. And correct too.
     
  6. Oct 15, 2011 #5

    phinds

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    ogward, I gotta tell you I almost had a heart attack when I looked at your first circuit diagram. My mind absolutely rebelled and I felt like making the sign of the cross to ward off evil (and I'm not even religious).

    THAT'S the kind of response you're likely to get from an EE prof if you draw your circuits right to left. :smile:

    (well, OK, I might be a BIT extreme)
     
  7. Oct 15, 2011 #6
    Hehe you are are probably right i just didn't like the Idea of heaving the MSB on the right side and the LSB on the left, made me a bit confused :P

    Thanks for your pointers!
     
  8. Oct 15, 2011 #7

    phinds

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    I'll be darned. It's been probably 35 years since I've designed those circuits but I DO remember now having exactly the same thought back when I started. You get used to it.
     
  9. Oct 15, 2011 #8

    LCKurtz

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    If you like the LSB flip-flop on the right, just put it there. What's the problem?
     
  10. Oct 16, 2011 #9
    I thought it wouldn't work that way so I didn't wanna experiment with something that works.
    But I've tried it and it works, no problems.
     
  11. Oct 16, 2011 #10

    lewando

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    Is the original problem stated correctly? If CP is being used as the clock input into the JK flip-flops and it is always high, how do the flip-flops change state (count)?
     
  12. Oct 16, 2011 #11
    I formulated it wrong, it should count when the CP goes from 0 to 1 as stated in the state diagram.
     
  13. Oct 16, 2011 #12

    lewando

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    Maybe I am picking nits (to get out of doing housework...), but the state diagram is not clear about CP going from 0 to 1 causing a state transition. If I read the state diagram literally, when CP is 0: stay in same state, when CP is 1: change state. So when CP is 1, the diagram says that the states are constantly changing. Apparently that is not what you want to do, but that is what the diagram is saying (to me, anyway). I would propose adjusting your notation somehow to indicate if CP is either a 0 or a 1: stay in same state, if there is a transition from 0 to 1 (perhaps a rising edge symbol) go ahead and change state.
     
  14. Oct 16, 2011 #13

    LCKurtz

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    Of course JK flip-flops change state at the falling edge of the clock. I wondered about the "only change state when the CP is high" too. That doesn't make sense to me for a clocked state machine using JK flip-flops. The proposed solution runs the counter downward counting on every clock pulse falling edge when i = 1 and pausing when i = 0.

    It seems like a correct solution to a poorly worded problem to me. Perhaps the OP will return with his teacher's comments later.
     
  15. Oct 16, 2011 #14
    You guys are right. It is probably poorly worded because I had to translate everything from swedish to english.
    And yes I can get back with my professors notes.
     
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