Design of interrupt handling hardware circuit for a real time scenario

[brainbaby]

TL;DR Summary

I want to design a hardware circuit for a library system which fetches books by maintaining a catalog of all books & referring the catalog each time the location of book changes. This ressembles to handling interrupts using Interrupt vector table.

Implementing interrupt handling mechanism using interrupt vector table for a daily life (real time) example.

I want to design a hardware which implements a logic of accessing books from a library system.
The library system contains 3 shelves, 3 racks on each shelf, & some books.
The aim of the circuit would be to fetch the desired book from the shelf based on using a catalog table. The catalog table consist of a catalog number & the book address. Each book has a unique catalog no. associated with it.

I have assumed two scenarios.
1st- Initial location of the books is made know to the CPU.
2nd- the book of interest which we want to access is stored to a new shelf.

Now this fetching can be achieved by two approaches:
1. Making the cpu remember the change of the location of a book each time when the location is changed will cost cpu resources & will be inefficient.
2. By maintaining a catalog table which is updated each time a book location is changed, the cpu just have to look at the catalog table & just have to execute a jump operation to directly fetch the desired book.
Approach 2nd is also called an interrupt vector table approach, which is easy, efficient, less complex & low resource consuming.

So I want to design a hardware circuit which makes use of a vector table to fetch the required book from the shelf. How should I proceed?

Those who are genuinely interested can refer the attachment pdf for further insight about the problem.

Thanks!!

 

[pbuk]

• Why do you think that an interrupt vector table is a good way to implement this?
• Do you think that it is any more efficient to update an interrupt vector table than any other lookup table?
• Do you think that it is any more efficient to search for an entry in an interrupt vector table than any other lookup table?
• What you propose would result in writing separate code to retrieve a book from S1R1, S1R2 etc. like this:
  [code lang=Python title=pseudocode]
  def retrieveABookFromS1R1:
  # code
  def retrieveABookFromS1R2:
  # code
  def retrieveABookFromS2R3:
  # code
  [/code]
  Can you think of any disadvantages to this approach?

 

[berkeman]

TL;DR Summary: I want to design a hardware circuit for a library system which fetches books by maintaining a catalog of all books & referring the catalog each time the location of book changes. This ressembles to handling interrupts using Interrupt vector table.

2nd- the book of interest which we want to access is stored to a new shelf.

Why would the book be misfiled out of its catalog number position? That is not how libraries are organized and run:

https://librarycompany.org/2020/05/14/sorting-books-the-library-way/

 

[brainbaby]

Why would the book be misfiled out of its catalog number position? That is not how libraries are organized and run:

I am just assuming, I need not to be precise about how the actual library is arranged. I have just taken an e.g of a hypothetical scenario. I would appreciate if you could explain in ref to the context.

 

[Baluncore]

I want to design a hardware which implements a logic of accessing books from a library system.

There are so many levels for the meaning of "design a hardware", that your problem is nothing to do with a table of jump vectors.

It seems to me, rather than a book library, you are designing something more like a tool carousel stack, for an NC machine.

Why does the word "hardware" appear in your question? What technology are you considering?

 

[DaveE]

I think your "hardware" is a generic computer. It will have a CPU, memory etc. How you chose to use them is a SW architecture question. Sorry, I know I'm not answering your question. It's kind of an odd format for a real engineering problem. It sounds a bit like a homework problem in that way. As a HW guy, I am 100% sure this is a SW problem. So, I'll reiterate...

Why does the word "hardware" appear in your question? What technology are you considering?

If you do want to explore a hardware implementation I would consider the technology you want to apply. Now days, this would be something like an FPGA or CPLD. These would be programmed with some RTL (Verilog, et. al.) and it would look a lot like SW anyway. The lines between digital HW and SW can be pretty fuzzy these days.

As a total aside, this reminds me of a simple controller I had to design in the late 1980's for a lab instrument. We had just finished a big project with a microcontroller where the SW was really, really late. So I was instructed to do this one without the SW guys and "no #$@ &@#% microprocessor". The problem was it had to sequence events and such. So, I built a state machine with a counter (program counter, LOL) a ROM look up table and just a few bits of RAM (made with a couple of flip-flop ICs). It was the worlds stupidest uC and could have been done with one tiny PIC processor. The ROM was programmed with a C program I wrote on my PC. It worked OK, but it looked weird and the manufacturing techs never figured out how it worked. But, yea, sure boss, a complete HW solution.

 

[.Scott]

My first comment is that it's really hard to follow what you expect the hardware to do and what you're expecting of the software.

At first I interpreted "a hardware" as a hardware logic circuit that you were designing. But on a reread, I think you are using the term "a hardware" to mean an embedded computer system.

There are both external interrupts (from peripheral devices outside of the CPU) and internal interrupts (from "INT" commands that can explicitly invoke an interrupt handler by number). Since the computer already has the list of books and their shelf numbers, it seems that you must be using internal interrupts. So the software will looks up the book number (B1) in your list and discover the shelf vector number - say 5 for S2R2. Then, per your design as I understand it, it would issue an "INT 5" to invoke the S2R2 handler.

With what I've said above and, perhaps, with what I describe below, I think you can flush out your design a bit better and describe it better as well.

Let's look at that ISR vector table. The size of each entry in that table will be the size of a memory address. Since we only have six shelves, the vector number can be held in 3 bits $V_2 V_1 V_0$. The CPU logic will then use this value to create an actual memory address of the ISR Handler address. Let's set up the CPU and memory as byte-addressable, with memory addresses requiring 4 bytes (32 bits). And we'll put the base address of our ISR vector table at 0xFFF00000. So the address of our handler will be at 0xFFF00000 + $V_2 V_1 V_0 0 0$. Notice that the vector number has been shifted left by two, multiplied by 4, to accommodate the 4-byte size of each handler address.

With the handler address in hand, the CPU will perform some context-switching chores and then jump to this address (ie, load the handler address into the Instruction Pointer register). Per your description, the handler will now "locate the book B1 in the library". But all that handler knows about is the shelf number. You haven't provided it with the book number at all. So, what exactly does it mean for it to "locate a book". Perhaps it is simply going to display a message saying "Your book is at S1R1". Perhaps you are holding the book number at a pre-arranged memory location.

Using C++, here's one of your alternatives. Make each of those "handlers" a subroutine that takes one argument, the book number. In C/C++, the declaration for one of those handlers might look something like "void HandleShelfS1R1(char *BookNumber);". In C++ terms, 'HandleShelfS1Rs' is of type "void HandleShelfS1R1(char *BookNumber);". Define ShelfHandler as a pointer to that type; create an array of that type (ShelfHandlerList) indexed by your vector number; and then call your handler with ShelfHandlerList[shelf_number](book_number);

 

[pbuk]

Using C++, here's one of your alternatives. Make each of those "handlers" a subroutine that takes one argument, the book number. In C/C++, the declaration for one of those handlers might look something like "void HandleShelfS1R1(char *BookNumber);". In C++ terms, 'HandleShelfS1Rs' is of type "void HandleShelfS1R1(char *BookNumber);". Define ShelfHandler as a pointer to that type; create an array of that type (ShelfHandlerList) indexed by your vector number; and then call your handler with ShelfHandlerList[shelf_number](book_number);

This would still be an anti-pattern, violating the DRY principle.

 

[.Scott]

This would still be an anti-pattern, violating the DRY principle.

The purpose of this "anti-pattern" is to provide the OP with something for comparison. I believe issue number 1 here is communication, not design. Issue number 2 will be what exactly are @brainbaby 's requirements. On the face of it, this is might be a pretty simple SW application. But the use of specialized circuitry might be an essential requirement.

I'm not sure if your "DRY principle" alludes to me mention of "C++" three times or to the design element I described.
If it's mention of 'C++': As best I can tell, the OP is not that familiar with C++. So without being explicit (and a bit repetitive), he would have a lot of room to misinterpret what I was saying. If I was addressing the same remarks to you, I would use more abbreviated language.

Or did DRY refer to the design element? It certainly caught my immediate attention that the Op wanted to call a different handler for each different shelf. It's easy to imagine that different shelves would require different processing. But most people would expect that if you've search one shelf, you've searched them all. So why not just have a table of shelf descriptors that a single shelf handler can use to find and check any well-described shelf?
I had not been attempting to present a full design, or even a partial design. For one thing, the information presented is too scant to nail down even the basic requirements of this system. More importantly, as mentioned above, a prime project requirement seems to center around the processing method itself - rather in the spirit of "I have a hammer. What can I build with this?".

 

[brainbaby]

what you expect the hardware to do and what you're expecting of the software.

The user should input the book name B1 & cpu accordingly search the book into shelves displaying an output telling the shelf & row info of the book, i.e "the book B1 is located in shelf 1 row 2" (just an e.g)

For software I mean to make min use of it as I am limited in C,C++ language, just being a beginner in computer architecture.

But on a reread, I think you are using the term "a hardware" to mean an embedded computer system.

I want to design the cpu for this specific purpose only, so yes you are right, an embedded computer system (which should have an Input unit, cpu & output display)

Perhaps it is simply going to display a message saying "Your book is at S1R1"

yes exactly!

Let's look at that ISR vector table. The..

case1:
let vector no be- 001 (shelf 1)

calculation of entry address: Shift Left by 2:
001
×
4
=
00100
(binary) which is 4 (decimal).

address calculation: 0xFFF00000 + 4 = 0xFFF00004

0xFFF00004 address is the entry address which contains the handler address

case 2:
now location of book B1 is updated to new location (eg in shelf 2)

so catalog table is updated, reflecting new vector no. for B1 which is 010

010
×
4
=
01000
(binary) which is 8 (decimal).

0xFFF00000 + 8 = 0xFFF00008

so the address 0xFFF00004 & 0xFFF00008 signifies the beginning of new shelf in the memory.
Difference between both the address is of 4, due to byte addressing.
Ok got it till here ...

Now, my query is how to implement all this calculation part in a logic circuit or to make a "no #$@ &@#% microprocessor" out of it @DaveE , a complete HW solution.

Now how should I begin?

 

[DaveE]

Now, my query is how to implement all this calculation part in a logic circuit or to make a "no #$@ &@#% microprocessor" out of it @DaveE , a complete HW solution.

FPGA.

 

[pbuk]

Or did DRY refer to the design element? It certainly caught my immediate attention that the Op wanted to call a different handler for each different shelf. It's easy to imagine that different shelves would require different processing. But most people would expect that if you've search one shelf, you've searched them all. So why not just have a table of shelf descriptors that a single shelf handler can use to find and check any well-described shelf?

This, because the code you end up with is something like:

[code lang=Python title=pseudocode]
interruptVector = [
*handleInterruptForS1R1,
*handleInterruptForS1R2,
*handleInterruptForS2R3,
];
def handleInterruptForS1R1():
bookTitle = getCurrentBookTitle()
display("The book " + bookTitle + " is located in shelf 1 row 1")
return
def handleInterruptForS1R2():
bookTitle = getCurrentBookTitle()
display("The book " + bookTitle + " is located in shelf 1 row 2")
return
def handleInterruptForS2R3():
bookTitle = getCurrentBookTitle()
display("The book " + bookTitle + " is located in shelf 2 row 3")
return
[/code]

Instead you want code that looks like this:

[code lang=Python title=pseudocode]
def retrieveABook(bookTitle, shelf, row):
display("The book " + bookTitle + " is located in shelf " + shelf + " row " row)
return
[/code]

 

[.Scott]

As I said, my purpose was to improve communications. Not to provide any kind of final design.

We now know that all he wants is to display a message. But the OP also wants "design a CPU for this specific purpose".

So, anyway, later tonight I will reread his posts and see if I can find the shortest path between what he's thinking of and what common HW/SW development tools and components are available.

 

[pbuk]

But the OP also wants "design a CPU for this specific purpose".

Apparently now they don't want a CPU-based solution.

Now, my query is how to implement all this calculation part in a logic circuit or to make a "no #$@ &@#% microprocessor" out of it @DaveE , a complete HW solution.

Clearly they don't know what they want, or what potential solutions are available and best suited to the problem at hand.

This is beginning to look like a homework problem: @brainbaby please tell us what is going on.

 

[.Scott]

At the core of the OPs system, there must be a table with two fields per entry, the book name and the shelf location. Such a table is much easier to use and maintain by software on a computer system that by custom hardware circuitry. For one thing, all the book names will be encoded as strings of characters - in the simplest cases, ASCII. Those strings can be manipulated directly by custom HW circuitry, but the primary result would be to make the project orders of magnitude more difficult.

Since that table is going to be maintained (as new books are added or shelf assignments change), it makes little sense to use specialized circuitry to use the table for querying shelf location. When a book query is performed, step one will be to read the book name - likely from keyboard input - which is best a job for software. Then the entry must be found in the table. If there is concern about how quickly this can be done, there are SW techniques (hashing, binary searches) that can make this search faster than your librarian can read the result. Once the table entry is discover, the shelf ID is available. Since all you want to do is display that ID, no specialized HW circuitry will be required - or would even be useful.

So, I think we need to focus on what you (the OP) are looking to accomplish. I very much doubt that this is a homework assignment - I just can't see someone interpreting any homework assignment such that it comes out looking like the OPs postings. So, I am guessing you are assigning this project to yourself because working this kind of HW circuitry is of interest to you (the OP).

If that is the case, please describe what you are looking for, what kind of experience you have, and what kind of resources are available to you - for example, what's you time and money budgets? Also, how interested are you in working with a computer? The reason I ask that is that any circuitry that interfaces to a CPU will require the use of computer applications (for example, minicom or PuTTY) and/or some custom SW development.

 

[brainbaby]

So, I think we need to focus on what you (the OP) are looking to accomplish. I very much doubt that this is a homework assignment - I just can't see someone interpreting any homework assignment such that it comes out looking like the OPs postings. So, I am guessing you are assigning this project to yourself because working this kind of HW circuitry is of interest to you (the OP).

True

please describe what you are looking for

I am interested in implementing computations directly into digital circuitry and converting algorithms into datapaths. Specifically, I aim to first design an algorithm for the current problem under discussion and then create a datapath for it

This is similar to an approach demonstrated by an author in his book: Digital Logic for Computing, John Seiffertt discusses the design and function of datapaths in computer systems.
For more details on this topic, refer to chapters 15 and 16, particularly pages 209 and 227 (Seiffertt, 2017).

Seiffertt, John. (2017). Digital Logic for Computing. 10.1007/978-3-319-56839-3.

I have provided a concise paraphrased excerpt from the book, which will help clarify my point effectively. Pls refer the attachment.

what kind of experience you have

I have a foundational understanding of basic switching theory and digital logic, which I learned during my college years. While I may need to review material to refresh my memory on certain concepts, I am familiar with the topics being discussed. I consider myself to be between a novice and an intermediate learner.

resources are available to you

Currently, I do not have any resources available.

what's you time and money budgets?

Since this is for my personal learning, the money budget is not a consideration.

Also, how interested are you in working with a computer?

Absolutely, I'm very interested, especially when it involves more than just traditional reading. I'm enthusiastic about building concepts into a functioning machine, even if it's just a simulation. This hands-on approach to learning is both engaging and rewarding.

As we know, computers have undergone significant evolution over the decades. For someone learning about computers today, the challenge often lies in understanding technology that falls in between the primitive beginnings and the latest advancements. This middle ground can be difficult to comprehend, especially when foundational knowledge is missing.

The foundation I'm referring to is the historical development of computers from scratch, followed by the integration of new technologies and incremental design improvements over the years. This progression has led us to the sophisticated machines we use today.

Without a solid grasp of how computers were initially developed and how each subsequent innovation built upon the previous ones, it becomes challenging to correlate different stages of computer technology. This lack of foundational knowledge can make it difficult for learners to fully appreciate the complexities and advancements in modern computing.

To bridge this knowledge gap, it's essential to study the entire trajectory of computer development. Starting from the basic principles and early designs, and then moving through each significant technological advancement, allows for a comprehensive understanding of how we arrived at our current state.

By recognizing the importance of this continuum, we can better appreciate the innovations that have shaped modern computers and gain a deeper understanding of the technology we use today.

I hope my explanations have now clarified my points.

 

[Rive]

To bridge this knowledge gap, it's essential to study the entire trajectory of computer development.

As I see the issue is that you actually mixing several different stages/levels of that process into a single task already.

Interrupt handling came at a point when there was already a sufficiently developed hardware, and fixing it into some library system is already programming, while what you want at HW logic level is not much more than a plain RAM read/write (store/recall) process.

I think you should just take a look at actual old hardware (plenty of Intel 4004 documentation is available these days) or actual new hardware (PIC 12Fxx series is a magnificent study object for this) or at some build-your-own CPU projects (there are plenty of them: relays, logic ICs, FPGA - everything goes, even excel ) instead. That would give you insights into the workings of CPUs both at logic and machine code level, so you could properly connect it to the abstractions of programming level.

The way you started this grants only headaches, and not just for you.

 

[pbuk]

As I see the issue is that you actually mixing several different stages/levels of that process into a single task already.

This.

I am interested in implementing computations directly into digital circuitry and converting algorithms into datapaths.

OK, we now understand your goal.

Specifically, I aim to first design an algorithm for the current problem under discussion and then create a datapath for it

The "current problem under discussion" will not take you towards your goal: it is not possible to explain to you why not because you don't know what you don't know, but this is what everyone posting in this thread is trying to tell you.

This is similar to an approach demonstrated by an author in his book: Digital Logic for Computing, John Seiffertt discusses the design and function of datapaths in computer systems.
For more details on this topic, refer to chapters 15 and 16, particularly pages 209 and 227 (Seiffertt, 2017).

Seiffertt, John. (2017). Digital Logic for Computing. 10.1007/978-3-319-56839-3.

I have looked at that book, it looks pretty good. Here is an example exercise from chapter 16 (extract from DOI 10.1007/978-3-319-56839-3 © Springer International Publishing AG 2017):

• 16.1 Design a datapath that can Fetch, Decode, and Execute the following
  instructions.
  

  MOV X, #N       Store the value N in register X
  MOV Y, Rn       Copy the value from Rn into register Y
  MOV Rn, X       Copy the value from register X into Rn
  ADD Rn, X, Y    Add X + Y and store the sum in Rn
  SUB X, #N       Subtract X - N and store the result in X
  XOR X, Y        Compute the bitwise XOR of X and Y and store the result in X

  
  Label all your control signals, use the values from the instruction encoding when possible, and do not include unnecessary connections. You may use all of our digital components, including a register file and a single ALU

That is a suitable problem for designing a datapath.

In later chapters you will learn how to design a datapath for a general purpose CPU. If you want to build a self-contained device to receive inputs (of book reference numbers), look up their location and present it on a display then a general purpose CPU is the best solution. (Aside: why do you think that a dedicated logic array would not be a good solution for this?)

I'm very interested, especially when it involves more than just traditional reading. I'm enthusiastic about building concepts into a functioning machine, even if it's just a simulation. This hands-on approach to learning is both engaging and rewarding.

You could build such a system (and learn a lot more besides) using an Arduino starter kit such as this one.

 

[berkeman]

Thread closed for Moderation.

 

[berkeman]

This thread started badly, with the OP trying to fit a square peg into a round hole. It has gotten worse, with the OP using an AI Chatbot to try to help fill out their replies. That is explicitly against the PF rules, which the OP has been reminded of via PM. Thread will remain closed; thanks to all who tried to help the OP with their ill-conceived project.