Designing a CPU Using Multimedia Logic - Need Advice

  • Thread starter Thread starter Basher1
  • Start date Start date
  • Tags Tags
    Logic
Click For Summary

Discussion Overview

The discussion revolves around the design of a simple single cycle CPU intended to implement a sorting algorithm using a software called Multimedia Logic. Participants express their experiences and challenges with the software, its limitations, and the design process involved in creating a CPU.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Homework-related

Main Points Raised

  • One participant describes their task of designing a CPU using Multimedia Logic but expresses uncertainty about how to effectively use the software due to its lack of documentation.
  • Another participant asks for clarification on what "multimedia logic" entails, indicating unfamiliarity with the term.
  • A participant explains that Multimedia Logic is used for designing and simulating logic circuits but struggles to find proper documentation for its use in processor design.
  • Some participants compare Multimedia Logic to Xilinx's ISE design tools, suggesting that Xilinx offers more flexibility and resources for FPGA/CPLD design.
  • One participant argues that the restrictions of Multimedia Logic hinder their ability to implement certain design features, such as program flow changes, which they could easily manage in Xilinx ISE.
  • Another participant notes that while MUX components exist in Multimedia Logic, they are limited to bit lines and do not allow for bus switching, which complicates the design process.
  • A participant acknowledges their inability to assist with the software but recognizes the expertise of others in the discussion.

Areas of Agreement / Disagreement

Participants express a general consensus on the limitations of Multimedia Logic and the challenges it presents in CPU design. However, there is disagreement regarding the suitability of the software compared to more established tools like Xilinx ISE, with some participants defending Multimedia Logic while others criticize it.

Contextual Notes

Participants mention specific limitations of Multimedia Logic, such as the inability to switch buses and the lack of comprehensive documentation, which may affect their design capabilities. There are also references to varying levels of experience with different design tools among participants.

Basher1
Messages
27
Reaction score
0
I have recently been commanded with the task of designing a simple single cycle CPU to implement a sorting algorithm. We must design the project using multimedia logic. I have an idea how to design the processor, but I have no idea how to use this software. From my basic understanding of it, it doesn't allow me much flexibility. I've tried googling how to go about designing CPU's with this software, however it's grossly underdocumented(to my knowledge). Is there anyone with knowledge of this software??
 
Physics news on Phys.org
Basher1 said:
I have recently been commanded with the task of designing a simple single cycle CPU to implement a sorting algorithm. We must design the project using multimedia logic. I have an idea how to design the processor, but I have no idea how to use this software. From my basic understanding of it, it doesn't allow me much flexibility. I've tried googling how to go about designing CPU's with this software, however it's grossly underdocumented(to my knowledge). Is there anyone with knowledge of this software??

Can you please say a bit more about what "multimedia logic" is? I'm not familiar with the term yet. :smile:
 
apologies, Multimedia logic is software that is used to design and simulate logic circuits. I am interested in using it to design a processor but I can't find any documentation on how to use this software correctly
 
Basher1 said:
apologies, Multimedia logic is software that is used to design and simulate logic circuits. I am interested in using it to design a processor but I can't find any documentation on how to use this software correctly

Do you mean like Xilinx's ISE design tools? Their WebPack version is free:

http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm

You use this to design the FPGA/CPLD parts that make up your system. There are lots of FPGA/CPLD design tutorials on the web based on RTL or Verilog or VHDL hardware design languages. There are probably courses also offered at your local community college on this type of design tools, if that helps.
 
Basher1 said:
No, i know how to use project navigator but we can't use it in this project. here is the link for the software homepage. http://www.softronix.com/logic.html

Looks spammy to me. Why in the world would you be required to use those tools instead of being able to use professional-grade free design software from an industry leader like Xilinx?

And how is this spammy looking design software different from Xilinx's ISE? If you can use the Xilinx software, you should be able to use simpler tools like this, IMO.
 
@ berkeman: I'm curious why you think this is spammy software? Looked ok to me, but I didn't install it.

Designing logic with schematics is so old-school. Is it an old school? An old teacher?

Aside from that, would you know how to design a cpu from scratch using Xilinx ISE? The process isn't much different.
 
Because not everyone else who is doing this unit has got expierience with Xilinx ISE. The reason I find it difficult is there is too many restrictions on what you can do with the components. For example, I created a 16-bit Instruction memory by placing two generic 8-bit memory components side by side, I connected their data inputs and write enable lines to ground(since you don't write to IM unless its being programmed), then I connected a counter to the address inputs of the IM and loaded it with a sample program. This gave me a nice sequential program flow. But what if I want to change program flow(like with a branch)?. In Xilinx ISE I would probably add an 8-bit 2:1 Mux. In this there is no 8-bit 2:1 Mux, I would need another way. ISE gives virtually no limitations except what is physically achievable whereas in the logic simulator you are limited by restrictions of the software. This would be fine if I could find some documentation on the software but I can't. Yeah I guess the Teacher is old school, but my university has really good facilities.
 
There are MUX's but they are all bit lines, you cannot switch buses, there is a bus tool, again they are all bit lines. I can't for the life of me figure out how that is useful, and I'm guessing there is some approach to designing processors in this software but if there is I haven't found it.
 
  • #10
Sounds like you know what you are doing. I can be of no help with the tool. Sorry.
 

Similar threads

Design of interrupt handling hardware circuit for a real time scenario
  • · Replies 19 ·
Replies
19
Views
3K
Designing a 2-bit Comparator with NOR gates
  • · Replies 7 ·
Replies
7
Views
8K
Design a Digital Stopwatch: Advice & Components Needed
  • · Replies 23 ·
Replies
23
Views
5K
I could really use some help picking my optional module [GameDev]
  • · Replies 2 ·
Replies
2
Views
3K
Engineering Designing an adjustable voltage source using only resistors and a pot
  • · Replies 10 ·
Replies
10
Views
3K
Engineering Full adder circuit using NAND v NOT, AND, OR v PLA logic
  • · Replies 1 ·
Replies
1
Views
5K
Engineering How do I model a Thorium Reactor thermal system?
  • · Replies 7 ·
Replies
7
Views
2K
Logic Design: Interpreting entering and leaving a room.
  • · Replies 10 ·
Replies
10
Views
4K
Need help with a mod-6 counter using JK flip flops w/ control bit
  • · Replies 1 ·
Replies
1
Views
3K
How Can You Simplify Boolean Expressions Using Only NOR Gates?
  • · Replies 2 ·
Replies
2
Views
2K