Full adder circuit using NAND v NOT, AND, OR v PLA logic

  • Engineering
  • Thread starter Bourbon daddy
  • Start date
  • #1
I have designed a full adder circuit, first of all implementing NOT, AND, OR logic, then redesigned NAND logic and finally Programmable Logic Array.

I would like to talk evaluate my designs a little and need a bit of help.

When using NOT, AND, OR gates I used the following;

NOT x 3 = 1 chip
AND x 11 = 3 chips
OR x 5 = 2 chips

Total 6 chips required

Using NAND Logic, I think I originally used 40 NAND gates, but reduced it to 26, so 7 chips would be required.

PLA:

NOT x 3 = 1 chip
AND x 7 = 2 chips
OR x 2 = 1 chip

Total 4 chips required.

Obviously, PLA offers the best solution for this scenario regarding efficiency, cost, speed and reliability.

I was wondering if using just one type of chip, such as the NAND offers any benefits to using various types of chip(NOT, AND and OR). If not, am I right in thinking that in this situation, using NAND logic offers no benefits to this circuit over NOT, AND, OR logic.

Regards
 

Answers and Replies

  • #2
berkeman
Mentor
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I have designed a full adder circuit, first of all implementing NOT, AND, OR logic, then redesigned NAND logic and finally Programmable Logic Array.

I would like to talk evaluate my designs a little and need a bit of help.

When using NOT, AND, OR gates I used the following;

NOT x 3 = 1 chip
AND x 11 = 3 chips
OR x 5 = 2 chips

Total 6 chips required

Using NAND Logic, I think I originally used 40 NAND gates, but reduced it to 26, so 7 chips would be required.

PLA:

NOT x 3 = 1 chip
AND x 7 = 2 chips
OR x 2 = 1 chip

Total 4 chips required.

Obviously, PLA offers the best solution for this scenario regarding efficiency, cost, speed and reliability.

I was wondering if using just one type of chip, such as the NAND offers any benefits to using various types of chip(NOT, AND and OR). If not, am I right in thinking that in this situation, using NAND logic offers no benefits to this circuit over NOT, AND, OR logic.

Regards
Why is the PLA solution a multi-chip solution? You should be able to do it all in one PLA IC of some modest size. Which PLA did you target?
 

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