Designing a synchronous counter

Click For Summary
The discussion focuses on designing synchronous counters using J-K flip-flops, specifically an up counter that counts 0, 2, 4, 6, 8, 10, 12, 14, 0 and a down counter from 9 to 0. Key points include the need for all J-K flip-flops to be in toggle mode, utilizing AND gates to control the toggling based on preceding flip-flop outputs. The distinction between the up and down counters lies in the input fed into the AND gate, with the up counter using the Q input and the down counter using the inverted Q input. The user is seeking assistance on merging the up and down counters with a control input after developing the necessary truth tables and flip-flop excitation tables. The conversation emphasizes the importance of a systematic approach to design and control in synchronous counter circuits.
xtb789
Messages
1
Reaction score
0
Hi everyone. There are 2 questions i cannot solve here. So i am hoping someone here can help me out. Here are questions:

(1) Design a synchronous counter using J-K flip flops which will count
through the sequence 0, 2, 4, 6, 8, 10, 12, 14, 0.

(2) Design a synchronous down counter using J-K flip flops which counts
backwards from 9 down to zero.
 
Physics news on Phys.org
When designing a sync counter. You need to remember that the clock signal hits all the JK FF at once as opposed to a async counter (where the output of one FF is the clock for the other). Remember that all JK must be in toggle mode. We enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are "high." To do this we need AND Gates. Read http://www.allaboutcircuits.com/vol_4/chpt_11/3.html and then you may be able to build your counters. It also schematic diagrams for a few counters that you can reference.

One difference between the up and down counter, is the input that's fed into the AND Gate. For a up counter the Q input is fed into the AND Gate and for the down counter the Q(inverted) input is fed into the AND GAte.
 
Last edited:
i'm trying to find out how to design a synchronous up/down counter using JK Flip Flops. Counting up in the sequence 1,3,5,7,4,2 and down count 2,4,7,5,3,1. Also i would like to know how the control input will be connected to the counter?...
 
Start by making a table of : Input and Present-State versus Next-State. This is called the state transition table.

Next you work out what values of J and K are required to make the above transitions. These truth tables (or k-maps) are called the flip-flop excitation tables (maps).

For optimal design don't restrict the JK flip-flops to only toggle function but use the following assignments to determine your flip-flop excitation.

Code:
PS NS   J K (comment)
0  0    0 X (no change or reset)
0  1    1 X (set or toggle)
1  0    X 1 (reset or toggle)
1  1    X 0 (no change or set)
 
Up/down counter

Yeah...I've done all of that and got this.

Up counter>>...Ja=C'+B Ka=BC Jb=A+C Kb=1 Jc=AB Kc=A'
Down Counter>>...Ja=B'C Ka=B'C' Jb=1 Kb=A+C' Jc=A'B Kc=A'B+AB'

Now I'm stuck on how to merge the up and down counter with the control input....please help!
 

Similar threads

  • · Replies 3 ·
Replies
3
Views
2K
  • · Replies 1 ·
Replies
1
Views
4K
Replies
1
Views
3K
  • · Replies 5 ·
Replies
5
Views
4K
  • · Replies 2 ·
Replies
2
Views
6K
  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 2 ·
Replies
2
Views
2K
  • · Replies 4 ·
Replies
4
Views
3K
  • · Replies 1 ·
Replies
1
Views
2K
  • · Replies 10 ·
Replies
10
Views
4K