Designing 3-Stage Async Counter & Logic Circuit in PSpice

[Jerremy_S]

Homework Statement

The block diagram of FIGURE 3 shows a three-stage asynchrononous counter that is used to count a series of randomly occurring input pulses. The ‘Q’ outputs of the counter are used to drive a logic circuit that gives the output shown in TABLE 1.

(a) Design the counter using type D flip-flops and simulate your design in PSpice, producing waveforms to confirm the circuit’s operation.

(b) Design the logic circuit to realize the desired ABCD outputs and simulate your design in PSpice, again producing waveform to demonstrate the circuit’s operation.

Homework Equations

The Attempt at a Solution

Hi, could you please help.

I managed to run simulation regarding a), but looking closer at Table 1 looks like the counter could be reset at Input Pulse 8 as the state of outputs start repeating itself. Would this be correct?

Thanks

 

[lewando]

You are correct in your observation. But the counter is not "resetting itself". It is simply going to the next state following state 7 (state 0).

 

[Jerremy_S]

Does it mean that using 10 different output states (0 to 9) as an input to the logic circuit would be a good approach?

 

[lewando]

With 3 D-flops, represented by their outputs Q1, Q2, and Q3 you can have only 8 distinct states.

 

[Jerremy_S]

Thanks! Just realized that! 2^3=8 states (0 to 7). Not sure how to decode 3 inputs into 4 outputs designing a logic circuit. Any hints?

 

[lewando]

Start by drawing a truth table for your Logic box. From there, you will construct 4 boolean equations, one for output D, one for C, and so on. Those equations can be simplified (if you want to minimize the number of logic gates needed to build) using boolean math or Karnaugh maps. I hope you have already been introduced to this. If not, you might have some self-study to do.