Drawing 4-2 Priority Encoder Circuits

  • Thread starter Salman Ali
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Salman Ali
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Hello guys! I am getting confused in drawing the circuit for a priority encoder. Because I saw some youtube videos and also on google , they all are drawing 4 to 2 priority encoder differently.These both are 4 to 2 priority encoders.
 
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  • Handwritten logic circuit diagram of a 4-to-2 priority encoder with inputs labelled 3, 2, 1, 0, using inverters, NAND and OR gates, and outputs labelled 2 and 1 with a 'Valid output' label.
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  • Logic circuit schematic of a 4-to-2 priority encoder with inputs I0 to I3 and outputs Y0, Y1 and Valid, built from OR gates, an AND gate and a NOT gate. Equations shown: Y1 = I2 + I3, Y0 = I3 + I2'I1, Valid = I0 + I1 + I2 + I3.
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Discussion

There are many ways of building a priority encoder using different logic gates. The particular technique will depend on polarity of the inputs, outputs and the technology employed. You should be able to design several other implications.
 
Here are three different examples of 8 input priority encoders.
Three logic gate diagrams of priority encoders: a 74LS147 decimal-to-BCD encoder, a 74LS148 octal priority encoder with enable inputs, and a CD4532B priority encoder schematic.
 
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