END;Solve 8-Digit Display Error in Boolean Expressions for Student ID Assignment

[ajbriggs]

I am designing a 7 segment display device to display an 8 digit number



The number is: 18008101. I'm using a 555 time circuit for the clock pulse which is connected form output (pin3) to input/clock (pin1) Lattice GAL22V10D, working fine as the number changes on every pulse. However the number being produced is incorrect. It currently displays '1' '8' '0' '0.(decPoint)' 'A' and the starts at '1' again. As shown in attached picture 24 is VCC, 12 is GRND and 14 - 23 are outputs to my 7 segment



Sorry about the following essay of code:

D1 D2 G F E D C B A
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 0
0 0 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 0
1 0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1 0
Next State
D1 D2 G F E D C B A
0 0 0 0 0 0 1 1 0
0 0 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 0
1 0 0 1 1 1 1 1 1
1 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 0 0

The two D pins (21,22) are not connected to the circuit they are used to tell the difference between the three different 1s and 0s and 2 different 8s in student ID.

So this is my design, can anybody tell me where I went wrong or which boolean expressions are incorrect.

TITLE ' Student Id Assignment '
DESIGNER ' Alex Briggs '
DATE ' '

Description
Counter to display student id number - 18008101
End_Desc;

PEEL22CV10A

CLK pin 1
RST pin 2

"I/O CONFIGURATION DECLARATION
"IOC (PIN_NO 'PIN_NAME' POLARITY OUTPUT_TYPE FEEDBACK_TYPE )
IOC ( 14 'A' Pos Reg Feed_Pin )
IOC ( 15 'B' Pos Reg Feed_Pin )
IOC ( 16 'C' Pos Reg Feed_Pin )
IOC ( 17 'D' Pos Reg Feed_Pin )
IOC ( 18 'E' Pos Reg Feed_Pin )
IOC ( 19 'F' Pos Reg Feed_Pin )
IOC ( 20 'G' Pos Reg Feed_Pin )
IOC ( 21 'D1' Pos Reg Feed_Pin )
IOC ( 22 'D2' Pos Com Feed_Pin )
IOC ( 23 '' Pos Com Feed_Pin )

AR NODE 25 "Global Asynchronous Reset
SP NODE 26 "Global Synchronous Preset

DEFINE

EQUATIONS

AR = !RST;

SP = 0;

"All Equations must end with semicolons.
"Internal or External output names appended with extensions:
" 1) .COM for Combinatorial Output
" 2) .D for D-type Registered Output
" 3) .OE for Output Enable Control


D1 = !D1&D2&!G&!F&!E&!D&C&B&!A+D1&!D2&!G&F&E&D&C&B&A

D2 = !D1&D2&F&E&D&C&B&A+!D2&!G&F&E&D&C&B&A

G = !D1&!D2&!G&!F&!E&!D&C&B&!A+&!D1&D2&!G&F&E&D&C&B&A

F = !D1&!G&!F&!E&!D&C&B&!A+&!D1&!D2&F&E&D&C&B&A+&!D1&!G&F&E&D&C&B&A

E = !D1&!G&!F&!E&!D&C&B&!A+!D1&!D2&F&E&D&C&B&A+!D1&!G&F&E&D&C&B&A

D = !D1&!G&!F&!E&!D&C&B&!A+!D1&!D2&F&E&D&C&B&A+!D1&!G&!F&E&D&C&B&A

C = !D1&!D2&!G&!F&!E&!D&!C&!B&!A+!D1&!G&!F&!E&!D&C&B&!A+!D1&F&E&D&C&B&A+!D2&!G&F&E&D&C&B&A

B = !D1&!D2&!G&!F&!E&!D&!C&!B&!A+!D&!G&!F&!E&!D&C&B&!A+!D1&F&E&D&C&B&A+!D2&!G&F&E&D&C&B&A

A = !D1&!G&!F&!E&!D&C&B&!A+!D1&!D2&F&E&D&C&B&A+!D1&!G&F&E&D&C&B&A

TEST_VECTORS
( [CLK,RST,I,Qg,Qf,Qe,Qd,Qc,Qb,Qa] -> [I,Qg,Qf,Qe,Qd,Qc,Qb,Qa] )
[0 1 X X X X X X X X ] -> [ X X X X X X X X ];
[0 0 X X X X X X X X ] -> [ L L L L L L L L ];
[C 1 0 0 0 0 0 0 0 0 ] -> [ L L L L L H H L ];
[C 1 0 0 0 0 0 1 1 0 ] -> [ H L L L L H H L ];
[C 1 1 0 0 0 0 1 1 0 ] -> [ L L H H H H H H ];
[C 1 0 0 1 1 1 1 1 1 ] -> [ L H L H H H H H ];
[C 1 0 1 0 1 1 1 1 1 ] -> [ L L L L L H H H ];
[C 1 0 0 0 0 0 1 1 1 ] -> [ L H L L H H H H ];
[C 1 0 1 0 0 1 1 1 1 ] -> [ H L L L L H H H ];
[C 0 1 1 1 1 1 1 1 1 ] -> [ L L L L L L L L ];

 

[jedishrfu]

The first thing that comes to mind is the list eqns to set the various variables based on the state of the variables. The classic Computer Science example is a simple number swap:

The first attempt is almost always:

X = Y
Y = X

The first assignment wipes out the value of X and the end result is that both values are Y's value. The correct solution is to use an intermediate variable T:

T = X
X = Y
Y = T

In your case, you may need a block temporary variables such as TD1, TD2, TG, TF ...

Hope this helps