Even and odd parity detector with active high/low inputs

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SUMMARY

The discussion focuses on designing a 3-bit active-low odd-parity detector using a single 74x138 decoder, one NOR gate, and one NAND gate. The output, labeled "P", will be logic 0 when there is an odd number of inputs (I2, I1, I0) set to logic 1. The confusion around active-low and odd parity is clarified: the output is active when the number of logic 1 inputs is odd, resulting in a low output. The discussion also contrasts this with scenarios involving active-high outputs.

PREREQUISITES
  • Understanding of 74x138 decoder functionality
  • Knowledge of active-low and active-high logic levels
  • Familiarity with parity concepts in digital logic
  • Basic experience with logic gates (NAND and NOR)
NEXT STEPS
  • Study the operation of the 74x138 decoder in detail
  • Learn about designing parity checkers in digital circuits
  • Explore the differences between active-low and active-high logic systems
  • Investigate the implementation of combinational logic circuits using NAND and NOR gates
USEFUL FOR

Electronics students, digital circuit designers, and anyone interested in understanding parity detection in digital systems.

thrainbow
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Homework Statement


Using a single 74x138, build a 3-bit, active-low, odd-parity detector. (Y0-Y7 are selected by "b2 b1 b0" in binary. Also the nibble "0 0 0" is considered even parity) You may use one NOR gate and one NAND gate, with arbitrary fan-in(>1). Label input variables "I2 I1 I0" and output variables "P".

Homework Equations


I'm just very confused about the fact that it's active low and odd parity. Does that mean the output will be a 1 for all of the inputs that have an odd number of 0's? What would happen if it was active low/even parity, active high/even parity, or active high/odd parity? Please help me to understand.

The Attempt at a Solution


I am thinking that I need to look for all inputs that have an odd number of 0's and the output P will be a 1. But I am not entirely sure about the answer. Also, to connect all of the outputs to a NAND gate and then to a NOR gate?
 
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thrainbow said:
active-low, odd-parity detector
thrainbow said:
Does that mean the output will be a 1 for all of the inputs that have an odd number of 0's?

No this just refers to the output pin. Break that down...

It's an "odd-parity detector" so the output will be ACTIVE when an odd number of inputs are logic 1.
The output is "active-low" which means the output will be logic 0 when ACTIVE.
So all together..
The output will be Logic 0 when an odd number of inputs are logic 1.

If the output had been described as "active-high" then the output would have been logic 1 with an odd number of logic 1's present.