Explanation of graphs involving capacitors (charging/discharging)

[Mutaja]

Homework Statement

I've tested the circuit above, when the switch is in the 2nd position (not the one on the picture) and got the below graph from the plotted data I received.

The capacitor C1 has been charged to 4V, and will start to discharge through R3.

I'll have to explain this graph in my report.

The blue graph is the discharging of C1, the green graph is the charging of C2 and lastly, the red graph is the voltage across R3.

Why is the green graph starting below 0 V? And why is the red line starting above 4V?

The x-axis of the graph represent the time axis, and the y-axis represent the voltage.

Homework Equations

The Attempt at a Solution

I believe that the capacitor C2 (green graph) is below 0 because it hasn't been short circuited (discharged properly). But why is it affecting the graph with negative voltage, and not positive?

Also, the voltage across R3 (red graph) I believe is affected by the negative voltage of the capacitor C2.

When the capacitor C1 starts to discharge, C2 will have no voltage across it. All of the voltage in this circuit will be across R1. How can the capacitor C2 be "charged" (from not being properly discharged) with negative value?

How can I explain this properly?

 

[jaytech]

Are they all supposed to be on the same plot? What I mean is, are they all being plotted simultaneously or are you just trying to superimpose three separate plots as one? If it's the latter, it could be that the Voltage amplitudes don't actually correspond. It would make sense to me that each capacitor limits at 2V as t gets larger if the total is 4V initially. Considering the capacitors are the same value, the voltage at t=0 in your plot should be evenly divided across the two.

You may be right that it's just the capacitor was not properly discharged initially.

 

[Mutaja]

Are they all supposed to be on the same plot? What I mean is, are they all being plotted simultaneously or are you just trying to superimpose three separate plots as one? If it's the latter, it could be that the Voltage amplitudes don't actually correspond. It would make sense to me that each capacitor limits at 2V as t geats large if the total is 4V initially. Considering the capacitors are the same value, the voltage at t=0 in your plot should be evenly divided across the two.

All the data is being logged simultaneously. It was all logged within the same session.

The voltage is evenly divided between the two capacitors, but one is starting at a negative voltage as shown by green line in the graph. This can be because the C2 capacitor wasn't properly discharged before use. Why, though, it the voltage across R3 starting at more than 4V? Can the not properly discharged C2 capacitor (meaning it initially has a charge of around 50mV or so (roughly estimated from the graph)) affect the circuit in such way that it gives 500mV extra to the R3? Can the C2 capacitor be charged with negative voltage, that the C1 capacitor has to "make up for" - therefore having to discharge more than 2V through R3?

I'm confused.

 

[jaytech]

Yes that is what appears to be happening. Since C2 is not fully discharged upon altering the switch, it looks to R3 and C1 as having a "negative" voltage. Remember that the reference voltage is 0V. The initial voltage at t=0 in the new configuration goes up to bring the total to 4V across R3 initially, and upon discharging, C2 discharges to just below 2V in order to compensate. If you had an initial 0V on C2, you would have seen both caps meet at 2V and the initial voltage across R3 as 4V.

 

[Mutaja]

The initial voltage at t=0 in the new configuration goes up to bring the total to 4V across R3 initially

This might be unnecessary, but the total voltage goes above 4V across R3.

This is because C2 isn't properly discharged,and the total voltage in the circuit is therefore V_c1 + V_c2 which equals V_R3, that again equals to just above 4V.

What I'm still confused about is why the voltage across C2 is negative. If it was identically above 0V as it is below now, I would've understood why R3 is above 4V (obviously, the graphs for voltage across C1 and C2 would've flattened out at just above 2V).

That would be logical, wouldn't it? It's charged with a small amount of voltage that affects the circuit. In my graph, C2 looks to be discharged beyond 0V, which frankly is impossible?

 

[jaytech]

It's all relative, that's what I'm saying. It isn't charged below 0V with respect to where the switch is initially. It appears charged with a positive V here. It's when you flip the switch to position 2 that it appears to be below 0V. This is because the relative voltage (ground) of the initial configuration remains the same in configuration 2. C₂ believes it has a "negative supply" with respect to this ground, but the total voltage on R₃ will still be V_c1 + V_c2 because that is the total voltage in the loop. The sign is a result of how the current appears from ground.

 

[Mutaja]

It's all relative, that's what I'm saying. It isn't charged below 0V with respect to where the switch is initially. It appears charged with a positive V here. It's when you flip the switch to position 2 that it appears to be below 0V. This is because the relative voltage (ground) of the initial configuration remains the same in configuration 2. C₂ believes it has a "negative supply" with respect to this ground, but the total voltage on R₃ will still be V_c1 + V_c2 because that is the total voltage in the loop. The sign is a result of how the current appears from ground.

Thanks so much for your help.

The only think I don't quite understand is how the relativity, or ground, can change with the flick of the switch. I think however I can find an explanation on that on google, so I won't bother you anymore.

Thanks for taking your time to explain this, I really appreciate it.

 

[NascentOxygen]

Mutaja, it does appear that your C2 started off with an initial negative charge. It is only small, but it's apparently there. I am mystified as to how it could come about, as being electrolytic capacitors, it is unlikely to have experienced a negative voltage in any properly operating circuit. Maybe the students who constructed the circuit in a class before yours had managed to get that cap around the wrong way and left it with reversed charge? Maybe your group failed to observe its correct polarity? A small positive charge remaining from previous use would be seen as negative charge if the cap was accidently reversed. With just 4 volts, a large electrolytic could possibly safely withstand reverse polarity for a short while...I like the thoroughness of your questioning. Keep it up!

 

[Mutaja]

Mutaja, it does appear that your C2 started off with an initial negative charge. It is only small, but it's apparently there. I am mystified as to how it could come about, as being electrolytic capacitors, it is unlikely to have experienced a negative voltage in any properly operating circuit. Maybe the students who constructed the circuit in a class before yours had managed to get that cap around the wrong way and left it with reversed charge? Maybe your group failed to observe its correct polarity? A small positive charge remaining from previous use would be seen as negative charge if the cap was accidently reversed. With just 4 volts, a large electrolytic could possibly safely withstand reverse polarity for a short while...


I like the thoroughness of your questioning. Keep it up!

Thank you, Sir. This was the explanation I went with, in addition to my own views and opinions I guess, but the way you explain it was very logical in my opinion.

Well, I think there's a fine line between being considered thoroughly (?) and annoying and repetitive But I'm glad you approve!

I've also had a bunch of work thrown in my face lately, so I haven't been able to reply quickly all the time, but I guess that's what a forum is for. Answer at your own speed.

Thanks again for your reply. It was refreshing to get other peoples view on this, and it helped me out a lot. I really appreciate it.