Frequency Counter Design: Help with Latch Function & 7-Segment Display

[malsch]

Homework Statement

Hi, I need to design a simple frequency counter to measure the frequency of a square wave input (hence signal conditioning is not needed for now). I have understood the concept that the counter needs to count the input pulses for 1 second and display them on a 7-segment. My problem is how am i going to use the latch function (LE) to keep showing the frequency that was counted.

The Attempt at a Solution

This is what I came up with so far:

The input signal (in this case 50Hz) triggers the 1Hz monostable, hence counts for 1 second. The problem is that after that 1 second, the counter resets to zero and recounts to 49 in this case. I need to find a way to keep the counter on 49 rather than going back to zero. Later I will add a 10Hz and 100Hz monostable for decimal points but for now I need to understand this concept.

Thank you.

 

[vk6kro]

You need about 3 control pulses and some careful timing to make a working frequency counter.

Firstly, a 1 second pulse from a 555 is not good enough. We all like these chips, but they are not capable of reliable time pulses.

You need to get an accurate 1 second pulse from a crystal oscillator driving some frequency dividers.

Then you use this pulse to count incoming pulses for exactly 1 second.
You can allow pulses to pass through a NAND gate while this 1 second pulse controls it.

Once the count is complete, you need to transfer the count to the display driver using a latch.
Then you turn the latch off. This makes the display show the final count of the counter until a new final count is available.

Then you need to reset the counter to zero. with a short pulse to the reset pins of the counter.

Then you start counting again after the reset pulse has gone.

 

[malsch]

yes i am now going to replace the 555 with a 1Hz crystal. What i cannot understand is how to use the latch function. What do you mean by control pulses? Ex. 1Hz, 10Hz and 100Hz? And what would you achieve by inputing the 1Hz and the frequency signal in a NAND gate?

 

[vk6kro]

Because this is in the Homework section, I can only give hints, not complete designs.

I can tell you about NAND gates, though.

The chip above has 4 NAND gates in it.

These have 2 inputs and one output. If both of the inputs have 5 volts on them, the output gets 0 volts on it.
If either input is low (ie at 0 volts) then the output will be 5 volts.

[PLAIN]http://dl.dropbox.com/u/4222062/NAND%20gate%20truth%20table.PNG

So, if I keep one of the outputs low (call it "A" to match the truth table above), it doesn't matter what happens to the other one ("B"), the output will be high.

If I keep this control input high for 1 second, any pulses that are applied to the other input will be passes to the output but they will be inverted. ie a high input will produce a low output and vice versa.

A latch chip will have one pin which will control the chip so that if it is high, the input of the latch will be passed through to the output, but if it is low, this won't happen. Or, it may be the other way around. You use Google to get a data sheet for the chip and look for the pin that does this.
In this case it would be the LE (latch enable) pin on the 4511.

Incidentally, crystals come in any frequency above about 30 KHz. To get 1 Hz out of such a crystal, you have to use frequency dividers (like the 74HC192s in your diagram). A frequency counter typically runs off a 10 MHz crystal, so you would have to divide by 10 million to get 1 Hz from such a crystal oscillator.

 

[malsch]

yes but if you have a 1 hz clock, when using the NAND gate, the counter counts for 0.5 seconds (since half the pulse is low and half is logic high)

 

[vk6kro]

Yes, that is right.
But I said:
"If I keep this control input high for 1 second, any pulses that are applied to the other input will be passes to the output but they will be inverted. ie a high input will produce a low output and vice versa."
That is not a 1 Hz signal. it is a 1 second pulse.

This is where the control circuit comes in.

Suppose you had a 4017 chip. Each time there is a rising edge on an input square wave, one of the outputs goes high. If the input frequency is 1 Hz, then the output will stay high for 1 second.

So, you could use one output for COUNT, one for LATCH and one for RESET, just by taking different outputs to the different parts of the counting circuit.
Only the COUNT output really needs to be an exact 1 second pulse, but it just wastes a little time to give exact 1 second pulses to the other outputs.

To avoid stepping through all 10 outputs of the 4017, you could take the next output after the RESET one back to the 4017's reset pin, so the 4017 starts the COUNT cycle immediately

 

[Quinzio]

The problem is that after that 1 second, the counter resets to zero and recounts to 49 in this case. I need to find a way to keep the counter on 49 rather than going back to zero. Later I will add a 10Hz and 100Hz monostable for decimal points but for now I need to understand this concept.

Thank you.

More than one had your problem before and they already implemented a solution.
The pin#5 of 74HC4511 does the latch function. If LOW, inputs are passed to display, if HIGH the display is frozen.
So the Q of NE555 must be passed to the LE of 74HC4511.
During the small period Q is low, data will be passed to display.
Then the counters must be reset AFTER the display has been updated.