How Do Pipeline Stages Affect Clock Cycles in CPU Processing?

[ver_mathstats]

Homework Statement

We have a 16-bit architecture which has a five stage pipeline for instruction execution, the five stages are: (a) fetch the next instructions, (b) decode the instructions and fetch operande, (c) perform ALU operation, (d) read or write to memory and (e) store the result in the register. Assuming each stage takes three clock cycles, how many instructions per clock cycle does the overall architecture execute? What would be the consequence of improving stage (a), (b), and (c) to process one instruction per cycle?

Relevant Equations

five stage pipeline

I think I am having trouble visualizing the count for the clock cycle. Would this just be the clock cycles divided by the instructions of the pipeline? I'm confused about how each stage of the pipeline takes three clock cycles to complete when there are five stages?

The consequence of improving stage (a), (b), and (c) is that the entire program will execute in about the same time? Is this the right idea?

Any help would be appreciated, thank you.

 

[Mark44]

Homework Statement:: We have a 16-bit architecture which has a five stage pipeline for instruction execution, the five stages are: (a) fetch the next instructions, (b) decode the instructions and fetch operande, (c) perform ALU operation, (d) read or write to memory and (e) store the result in the register. Assuming each stage takes three clock cycles, how many instructions per clock cycle does the overall architecture execute? What would be the consequence of improving stage (a), (b), and (c) to process one instruction per cycle?
Relevant Equations:: five stage pipeline

I think I am having trouble visualizing the count for the clock cycle. Would this just be the clock cycles divided by the instructions of the pipeline?

You have this backwards. Once the pipeline is full, all pipeline stages are executing at the same time. Again, when full, there are 5 stages operating every 3 seconds.

I'm confused about how each stage of the pipeline takes three clock cycles to complete when there are five stages?

Again, the five stages are operating independently.

The consequence of improving stage (a), (b), and (c) is that the entire program will execute in about the same time? Is this the right idea?

No. Speeding up the pipeline stages means that more instructions can be executed in less time.

Any help would be appreciated, thank you.

 

[pbuk]

No. Speeding up the pipeline stages means that more instructions can be executed in less time.

This is only true if later stages of the pipeline can be skipped if not necessary, otherwise stage (d) will become a bottleneck and one instruction per 3 cycles is still the upper bound.

 

[FactChecker]

This is only true if later stages of the pipeline can be skipped if not necessary, otherwise stage (d) will become a bottleneck and one instruction per 3 cycles is still the upper bound.

Exactly. And a mismatch at a bottleneck makes low-level programming much trickier. The results of the fast part of the pipeline would have to be grabbed and used before they were overwritten by the next calculation. That would force some sort of splitting of the fast results among multiple slower pipeline parts. This problem was central in programming array processors.

 

[Mark44]

This is only true if later stages of the pipeline can be skipped if not necessary, otherwise stage (d) will become a bottleneck and one instruction per 3 cycles is still the upper bound.

Right. What I was saying was more germane to arithmetic-type or similar instructions that don't have to access memory for reads or writes.

 

[ver_mathstats]

You have this backwards. Once the pipeline is full, all pipeline stages are executing at the same time. Again, when full, there are 5 stages operating every 3 seconds.
Again, the five stages are operating independently.
No. Speeding up the pipeline stages means that more instructions can be executed in less time.

So when trying to figure out the instructions per clock cycle, we would just be dividing the amount of instructions by the amount of clock cycles? Because the five stages operate independently?

 

[Mark44]

So when trying to figure out the instructions per clock cycle, we would just be dividing the amount of instructions by the amount of clock cycles? Because the five stages operate independently?

Any rate, such as instructions per clock cycle, can be thought of as a fraction:
$$\frac{\text{number of instructions}}{\text{number of cycles}}$$

 

[FactChecker]

Because the five stages operate independently?

I would not say it that way. The stages can run simultaneously, but they are not independent, they must pass the information along. So if one runs slower, the others must wait to supply or take the data to/from the slower stage. Things are simple when they are all running at the same rate but the second question of your post is more complicated.

 

[ver_mathstats]

I would not say it that way. The stages can run simultaneously, but they are not independent, they must pass the information along. So if one runs slower, the others must wait to supply or take the data to/from the slower stage. Things are simple when they are all running at the same rate but the second question of your post is more complicated.

Sorry that's not what I meant, I know they work together passing information along