DLX 5 stage pipeline processor execution and speedup

[Aviato78]

Homework Statement

Have a question related to the DLX 5 stage pipelined processor equipped with the forwarding technique. Have to draw pipeline execution drawing table of the instruction sequence and calculate the performance gain achieved by pipeling in terms of speed-up. Honestly confused on how to approach this question. Any help would be appreciated.

Relevant Equations

Equations I used in regards to finding the speed-up was Amdahls formula. Where speedup = old execution time / new execution time.

A 5-stage DLX pipelined processor is equipped with the
forwarding technique. The following code is executed in the
processor.
XOR R5, R5, R6 //R5=R5 XOR R6 (XOR: logic operation)

LW R1, 20(R5) //load word into R1

ADDI R1, R1, #2 //increment R1 by 2

SW 20(R5), R1 //store the content in R1 to memory

ADDI R5, R5, #1 //increment R5 by 1

OR R6, R6, R5 //R6=R6 OR R5 (OR: logic operation)

Draw the pipeline execution timing table of the instruction
sequence given above, with marked stalls and forwardings needed
to achieve a hazard-free pipeline for the most efficient performance
in terms of average CPI (the number of clock cycles used for
executing one instruction).
Calculate the performance gain achieved by the pipelining in terms
of speed-up. State any assumptions made in your calculation.

 

[berkeman]

Welcome to the PF.

Per the PF schoolwork rules, you must show us your attempt at the solution of the problem before we can offer tutorial help. Please do your best to start working on the problem -- show us what you know so far...

 

[Aviato78]

 

[Aviato78]

@berkeman Apologies have provided both solutions each relating to a part of the question.