How Do You Design a JK Flip-Flop Synchronous Up/Down Counter?

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Discussion Overview

The discussion revolves around designing a synchronous up/down counter using J-K flip-flops, specifically to count through a non-standard sequence. Participants explore the logic design required to achieve the specified counting sequences and verify the self-starting nature of the counter.

Discussion Character

  • Homework-related
  • Technical explanation
  • Debate/contested

Main Points Raised

  • One participant presents the exam question and expresses uncertainty about modifying an existing circuit designed for a different counting sequence.
  • Another participant suggests that three bits are needed and discusses the toggling behavior of J-K flip-flops, indicating that the arrangement of AND gates will need to change.
  • A participant expresses frustration over their failed exam and the complexity of their current solution, indicating a desire for a simpler approach.
  • One participant proposes creating a next state Karnaugh map table to derive the J and K inputs, suggesting this method could streamline the design process and reduce trial and error.

Areas of Agreement / Disagreement

Participants do not reach a consensus on the best approach to design the counter, with differing opinions on the complexity of the solution and the methods to be used.

Contextual Notes

Participants mention the need for multiple logic gates and the challenges of ensuring the counter is self-starting, but specific assumptions or definitions regarding the circuit design are not fully explored.

Mark200
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Exam question:

Use J-K flip-flops to design the logic for a synchronous up/down counter that counts "up" through the sequence 1 2 6 3 5 7 f the input switch UP is 1, and "down" through the sequence 7 2 1 5 3 6 if UP is 0. Verify that the counter is self-starting.


What I know so far:

Ok so in my book I've found a similar circuit, except it's to count through the sequence 1 2 3 4 and so on. And I'm not sure at all how I'd go about changing the circuit to work for the question above. The circuit I have is:

article1.sync_bin_c.gif


Any ideas?
 
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Hi Mark200, welcome to PF!

Hmmm...so it looks like you'll need three bits. And you want to go through the sequence:

001
010
110
011
101
111

It looks like the circuit you have makes great use of the fact that setting J = K = 1 toggles Q to change state, and setting J = Q = 0 keeps it the same. So I would expect that what would change would be which output of which AND gate goes where. That's all I've got though, short of actually trying to draw out different circuits.
 
Ok I'm afraid I'm going to need to ask for more help on this question! I failed my exam and I have to do a repeat exam, and it's tomorrow hah. And this question came up on the original exam!

I've been trying to figure out how to do it. I found a way, but it involves having about three logic gates for every single input and it's extremely messy. There must be an easier way. I tried to scan my work so far in but my scanner isn't working! I've thought about changing where the outputs go but I don't think that'll work.

Any ideas?? As much help as possible would be great! Even if it doesn't come up on the exam tomorrow it'd just be a relief to finally know how to do this question
 
Mark200 said:
Exam question:

Use J-K flip-flops to design the logic for a synchronous up/down counter that counts "up" through the sequence 1 2 6 3 5 7 f the input switch UP is 1, and "down" through the sequence 7 2 1 5 3 6 if UP is 0. Verify that the counter is self-starting.


What I know so far:

Ok so in my book I've found a similar circuit, except it's to count through the sequence 1 2 3 4 and so on. And I'm not sure at all how I'd go about changing the circuit to work for the question above. The circuit I have is:

article1.sync_bin_c.gif


Any ideas?

Mark200 said:
Ok I'm afraid I'm going to need to ask for more help on this question! I failed my exam and I have to do a repeat exam, and it's tomorrow hah. And this question came up on the original exam!

I've been trying to figure out how to do it. I found a way, but it involves having about three logic gates for every single input and it's extremely messy. There must be an easier way. I tried to scan my work so far in but my scanner isn't working! I've thought about changing where the outputs go but I don't think that'll work.

Any ideas?? As much help as possible would be great! Even if it doesn't come up on the exam tomorrow it'd just be a relief to finally know how to do this question

I'm sure it's a bit late for your exam. But instead of trying to find some ad-hoc jerry-rig that works, why don't you make a next state karnaugh map table with variables s, y0,y1,y2 from which you can solve for the J and K inputs? Takes a little time but also removes all the trial and error guesswork.
 

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