How does the D flip-flop in ADS 2008 frequency divider design work?

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genxium
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This component is from the ADS 2008 example(in Frequency Divider by 2, Design Guide), I don't quite understand how it works clearly.

By far I think that if D=0&CLK=1 , then the collector current Ic of BJT1 is small, resulting in that Vc of BJT1 is High, hence Vb of BJT14 is High and BJT14 is active, so [itex]\bar{Q}[/itex]=1.

But I have no idea how to figure out Q when D=0&CLK=1, can anyone give me a hint? I want to ask if the 2 left most BJTs with collector resistor are working as inverters?
 
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I can't see how this circuit would hold a value as the tail current is shared between the diff amps. One of them has to loose their bias depending on the state of clk. If I am right and it cannot hold a value it is not a flop.

Who labeled the inputs? My guess is that this is a comparator with an offset trim and hysteresis.

I only looked at this really fast so I could be totally off base though.
 
Actually, you know what. I think clk and nclk are supposed to be a select. You either select between a normal diff amp or a diff amp with both its inputs tied high.

I was thinking the other structure was for calibration or something but then I realized the bias is 1mA and the resistors and it dawned on me that this is not an IC.

I have no idea why one would do this though.