- #1
saad87
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I'm looking for some advice regarding how to terminate SPI signals which are going to an external PCB. I know that SPI isn't meant for board to board communication but in this case the connecting ribbon cable is short - about 6" max length.
My frequency isn't high, just 2 MHz but I have rising edges of about 4-7 ns which are causing issues. Here's what I'm thinking for in the next revision of the board: the "main" PCB needs to connect to 4 external PCBs each of which has two SPI slaves. I'm using a 10 wire ribbon cable and I should have each alternating wire has a ground.
To route SCK and MOSI I have a buffer just before the off board connectors. This dual buffer buffers SCK and MOSI. Each output drives a max. of two SPI slaves (because there's a buffer per PCB). Right at the buffer I have a source terminator resistor whose value I intend to find empirically. To illustrate:
MOSI and SCK from uC -> Buffer -> Ribbon Cable to nth PCB -> SCK and MOSI drive two SPI slaves.
So far so good - the slaves are located fairly near to each other so I think source termination will work OK here for both MOSI and SCK.
My main concern is regarding MISO. How do I effectively route and terminate this line? There's just one load (the master) but several slaves. Do I use source termination for this as well? Each slave could have a source resistance and the traces can join at some point on the slave PCB and then travel via the ribbon cable to the master. To illustrate:
Slave #1's MISO -> Source Resistor ___________________________ -> Ribbon Cable.
Slave #2's MISO -> Source Resistor ______________|
The ____ represents the trace on the PCB.
Note: I have already tried to slow down the rising edges on the current revision via series resistances. This works well but only to an extent. I feel I should make the effort to have proper termination on the next revision of the board.
My frequency isn't high, just 2 MHz but I have rising edges of about 4-7 ns which are causing issues. Here's what I'm thinking for in the next revision of the board: the "main" PCB needs to connect to 4 external PCBs each of which has two SPI slaves. I'm using a 10 wire ribbon cable and I should have each alternating wire has a ground.
To route SCK and MOSI I have a buffer just before the off board connectors. This dual buffer buffers SCK and MOSI. Each output drives a max. of two SPI slaves (because there's a buffer per PCB). Right at the buffer I have a source terminator resistor whose value I intend to find empirically. To illustrate:
MOSI and SCK from uC -> Buffer -> Ribbon Cable to nth PCB -> SCK and MOSI drive two SPI slaves.
So far so good - the slaves are located fairly near to each other so I think source termination will work OK here for both MOSI and SCK.
My main concern is regarding MISO. How do I effectively route and terminate this line? There's just one load (the master) but several slaves. Do I use source termination for this as well? Each slave could have a source resistance and the traces can join at some point on the slave PCB and then travel via the ribbon cable to the master. To illustrate:
Slave #1's MISO -> Source Resistor ___________________________ -> Ribbon Cable.
Slave #2's MISO -> Source Resistor ______________|
The ____ represents the trace on the PCB.
Note: I have already tried to slow down the rising edges on the current revision via series resistances. This works well but only to an extent. I feel I should make the effort to have proper termination on the next revision of the board.