How to increase max frequency due to half cycle constraints

In summary, the synchronous logic that uses a negative edge flop to shift data out of a chip has clock edge dependency issues that can limit the max clock frequency.
  • #1
flybanana
4
0
I'm trying to design a synchronous logic that uses a negative edge flop to shift data out of a chip (as part of the IEEE1149.1 standard). The input to this negedge flop is muxed from a whole bunch of shift registers within the chip, and these registers are all on posedges.

Ideally, if skew of clock signal between this negedge flop and the posedge flops that feed it is 0, then I know my max clock frequency is limited by
Tsetup of posedge flop + Tprop of input to output of posedge flop + Time to go through the mux + Tsetup of nedgedge flop.

However, some posedge register are situated far from the negedge flop physically on the chip, and in those cases, the clock for the posedge register is a delayed version of clock for the nedge flop, and that dramatically reduces my max clock frequency too.

Anybody have past experience designing this kind of logic and have suggestion as to how I can increase the the max frequency? (I can't want to change the clock edge dependcy of the flops)
 
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  • #2
If you want it to be fast, you shouldn't have long paths -- group the fast stuff toghether. Also, what does your clock tree look like?
 
  • #3
I'm not too sure what the clock tree look like (somebody else did that part), but the chip is quite big and has many partitions, so I believe we have an entry point into each partition and then branches out to different logic within the partition that needs the clock.

Also because of the large size of the chip, some of registers that I mentioned that feed the TDO(test data out) negedge register is situated far away from TDO itself. But all the registers do need to go out through the TDO pad, so I am not sure what I can do to "group the fast stuff together".
 
  • #4
How fast does your JTAG look so far in simulation? JTAG is not traditionally a blazing interface, mainly for the reasons that you are mentioning about the chip-wide nature of the scan chains.
 
  • #5
10mhz - which is typical at most companies I think, but I'd like to look into improving that, more specifically to see if there's anything I can do about the half-cycle limitation from the posedge->negege nature of flopping the values into the final TDO register.
Thanks for your help!
 
  • #6
So am I stuck with what I have? If anybody knows a methodology to do this, I'm much obliged. Thanks.
 

1. How does the half cycle constraint affect the maximum frequency of a signal?

The half cycle constraint refers to the minimum time required to complete one full cycle of a signal. This means that the maximum frequency is limited by the amount of time it takes for one complete cycle to occur. As the frequency increases, the time for one cycle decreases, and eventually, the signal cannot complete a full cycle within the given time constraint.

2. Can the maximum frequency be increased by reducing the half cycle constraint?

Yes, reducing the half cycle constraint can increase the maximum frequency of a signal. By decreasing the time for one cycle to occur, the signal can complete more cycles within the given time constraint, allowing for a higher maximum frequency.

3. What techniques can be used to increase the maximum frequency due to half cycle constraints?

One technique is to use a higher frequency clock signal to control the signal being generated. Another technique is to optimize the design of the circuit to reduce the time it takes for one cycle to occur. Additionally, using advanced components, such as high-speed transistors and integrated circuits, can also help increase the maximum frequency.

4. Are there any trade-offs when trying to increase the maximum frequency due to half cycle constraints?

Yes, there are trade-offs when trying to increase the maximum frequency. For example, using a higher frequency clock signal may result in increased power consumption and heat generation. Additionally, optimizing the circuit design may require more complex and expensive components.

5. How important is it to consider the half cycle constraint when designing a circuit with high frequency requirements?

The half cycle constraint is crucial to consider when designing a circuit with high frequency requirements. Ignoring this constraint can lead to circuit malfunction or failure, as the signal may not be able to complete a full cycle within the given time constraint. It is important to carefully optimize the design and choose appropriate components to meet the desired maximum frequency while also considering the half cycle constraint.

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