# Two-level NAND circuits plus ROM?

1. Mar 14, 2013

### asdf12312

two-level NAND circuits plus ROM??

1. The problem statement, all variables and given/known data
Code (Text):
We have three functions, X, Y, Z of the four variables, A, B, C, D. Note: Each part can be solved without the other:

X(A, B, C, D)= m(0,2,6,7,10,13,14,15)
Y(A, B, C, D) = m(2, 6, 7, 8, 10, 12, 13, 15)
Z(A, B, C, D) = m(0, 6, 8, 10, 13, 14, 15)

a. Implement with a two-level NAND gate circuit. This can be done using only prime implicants of the individual functions with 13 gates. With sharing, it can be done with 10 gates. Assume that all variables are available both complemented and uncomplemented.

b. Implement these functions using a ROM.

c. Implement this with 2 three-input (plus active low enable) decoders as shown here, plus a minimum number of AND, OR, and NOT gates.

T.T

solved the equations. (SOP)
X = A' B' D' + C D' + A B D + B C
Y = A C' D' + A B D + A' B C + B' C D' or
Z = B' C' D' + A B D + B C D' + A B' D'

what to do with this.

Last edited: Mar 14, 2013
2. Mar 17, 2013

### Staff: Mentor

Assuming these are correct, I guess you now implement X using 2-input NAND gates and signals A,B,C and D. (I think it means you also have A', B', etc. available and don't need to waste a gate to generate these yourself.) You'll first replace the ORs with NANDs.

I can't help with b or c.