Is Dynamic CMOS an Effective Method for Frequency Division?

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Discussion Overview

The discussion revolves around the effectiveness of dynamic CMOS as a method for frequency division, exploring its logic configurations and implications in circuit design. Participants share their understanding of dynamic MOS circuits, logic tables, and their experiences with related interview questions in the context of recruitment in engineering fields.

Discussion Character

  • Exploratory
  • Technical explanation
  • Debate/contested
  • Homework-related

Main Points Raised

  • One participant presents a logic table for dynamic CMOS but expresses uncertainty about its correctness.
  • Another participant notes the importance of considering multiple inputs to each stage in the logic table, suggesting a need for clarity in the relationships between variables A, B, C, and D.
  • A participant highlights the unique behavior of dynamic MOS circuits, where outputs can be in an open circuit state, affecting subsequent logic gates.
  • There is a discussion about the implications of specific input states on the output, with one participant questioning the accuracy of a proposed logic rule under certain conditions.
  • Several participants share their experiences with interview questions related to CMOS technology and express varying levels of familiarity with dynamic CMOS circuits.
  • One participant mentions plans to implement the circuit in Cadence to analyze the waveform and frequency, indicating a practical approach to understanding the topic.
  • A link to a resource on dynamic CMOS is shared, suggesting additional reading material for participants.

Areas of Agreement / Disagreement

Participants express differing levels of familiarity with dynamic CMOS circuits, and there is no consensus on the correctness of the logic rules presented. The discussion remains unresolved regarding the effectiveness of dynamic CMOS for frequency division.

Contextual Notes

Some participants acknowledge gaps in their understanding of dynamic CMOS circuits and express a need for further learning. The discussion includes references to specific circuit behaviors and logic configurations that may require additional context for clarity.

Who May Find This Useful

Students preparing for engineering interviews, individuals interested in CMOS technology, and those seeking to understand dynamic logic circuits may find this discussion relevant.

jaus tail
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Homework Statement
If input frequency is 4.35 GHz, what is output frequency
Relevant Equations
CMOS inverter theory. If Nmos has high gate voltage then Nmos conducts but if Pmos has high gate voltage, it turns off
245655

I made a table using excel as:
245656

D is output. Like this I get Output frequency is same as input frequency. But I'm not sure if this is correct.

PS: I'm aware I'm posting many questions, but I got interview exams coming up in August. Companies are going to come to university for recruitment and thus I'm brushing up my skills. Hope that's allowed...
 

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You seem to be missing the multiple inputs to each stage:
A depends on F and on C, C depends on B and on F.

I think you need to work out what the logic table is for these two (A, C) before you work out your table for A, B, C, D.
 
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You also need to note that this is a dynamic mos circuit, where gates can be neither high nor low (open circuit output) and the input to the next stage remains at its previous value, by retention of static charge on the gate.
 
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For logic table A = not(C) * not(F) not means inverted. * means 'and' gate
B = not(A)
C = not(F)
Output = not(C)

What do 'gates be neither high nor low' mean?
 
Say C was high and F was low, then N1 and P2 are off. P1 is on, but in series with P2 which is off. So the output A is open circuit, not connected to high nor to low. So A does not alter the gates of P3, N2 and N3. They hold their existing state (temporarily) due to the capacitance of their gate.
So the logic rule you gave, A=Not(C) And Not(F) is not necessarily correct when C=1 and F=0.

I have not worked with this sort of circuit, so I can't really help with the correct approach. I simply note that this is not a simple static logic circuit. My own (very old) CMOS text doesn't seem to mention these circuits.
Presumably, since you're being asked to analyse (or recognise) this circuit, you have come across this before.
 
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jaus tail said:
Problem Statement: If input frequency is 4.35 GHz, what is output frequency

...

PS: I'm aware I'm posting many questions, but I got interview exams coming up in August. Companies are going to come to university for recruitment and thus I'm brushing up my skills. Hope that's allowed...

Ask other students who’ve been through these interviews to see what kinds of questions they will ask. In the US, I seriously doubt they ask any kind of complex or detailed question rather ask about what you’ve studied, what areas you’d like to work in and what they have to offer. They would most likely take your resume and give you a call back or invite back for a more detailed interview if they’re interested.

I know in CS, there’s been a trend to ask odd questions to see how you'd might solve a particularly odd problem. Google was famous for those as well as Microsoft. I once had an interview where I was asked a C++ question which I had seen in a Dr Dobbs article on common interview questions.

I answered, mentioned the article and then asked another from it. The interviewer hadn’t heard of the article and couldn’t answer my question. I didn’t flunk him though, I just told him the answer and he was suitably impressed. Needless to say, I decided that wasn’t the company for me.
 
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I haven't come across this circuit. We've come across questions like: advantage of cmos over transmission gates, draw cmos for nand gate and nor gate.
given a logical expression: AB + (C (A + B) ). Draw its CMOS configuration.

My resume has a verilog project. I put more focus on that subject, than on VLSI. :)

Thanks for the guidance and help. The question is very difficult and exhausting. I'll try to implement it in Cadence to find the waveform and frequency.
 
If you know you have some defficiency then you should learn enough to tak about it and if pressed honestly say your familiar with and don’t it would be too hard to learn with your experience.

As an example, they are interested in Matlab but you have Mathematica experience then you’d prep yourself on Matlab so you can talk intelligently about its features and then connect your experience to it saying while I don’t have a working knowledge of Matlab with my Mathematica experience it shouldn’t be too difficult to pick up.
 
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Here's something on dynamic CMOS that I found recently and may be of interest to you:

http://www.eas.uccs.edu/~cwang/ECE5452_SOC/ECE5452_DynamicLogic.pdf
 
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